signal.cbx.xml

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.

<?xml version="1.0" ?>
<LOG_ROOT>
	<PROJECT NAME="signal">
		<CBX_INST_ENTRY INSTANCE_NAME="|signal|signal_gene:si|datarom:datarom_component|altsyncram:altsyncram_component" CBX_FILE_NAME="altsyncram_ki31.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|signal|signal_gene:si|lpm_divide:Div0" CBX_FILE_NAME="lpm_divide_g5m.tdf"/>
		<CBX_INST_ENTRY INSTANCE_NAME="|signal|signal_gene:si|lpm_mult:Mult0" CBX_FILE_NAME="mult_mk01.tdf"/>
	</PROJECT>
</LOG_ROOT>