signal.fit.summary

来自「yong VerilogHDL yu yan bianxie de pinlv 」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Sat Jun 07 13:50:26 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : signal
Top-level Entity Name : signal
Family : Cyclone
Device : EP1C3T144C6
Timing Models : Final
Total logic elements : 207 / 2,910 ( 7 % )
Total pins : 34 / 104 ( 33 % )
Total virtual pins : 0
Total memory bits : 4,096 / 59,904 ( 7 % )
Total PLLs : 0 / 1 ( 0 % )