signal.v

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.

//`include "signal_gene.v"
//`include "oclk.v"
//`include "key.v"

module signal(clk,rst,codekey,dataout,en,q_out);
    input clk,rst;
    input[7:0] codekey;
    output[7:0] en;
    output[7:0] dataout;
    output[7:0] q_out;
    wire clk10khz;
    
    oclk        oc(.clk(clk),.rst(rst),.clkout(clk10khz));
    signal_gene si(.clkin(clk10khz),.rst(rst),.control(codekey[1:0]),.i(codekey[7:2]),.q_out(q_out));
    key         ke(.clkin(clk10khz),.rst(rst),.datain(codekey),.dataout(dataout),.en(en));
endmodule