signal.qsf

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		signal_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C3T144C6
set_global_assignment -name TOP_LEVEL_ENTITY signal
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:23:14  MAY 27, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name VERILOG_FILE oclk.v
set_global_assignment -name VERILOG_FILE signal.v
set_global_assignment -name VERILOG_FILE signal_gene.v
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_location_assignment PIN_16 -to clk
set_location_assignment PIN_144 -to rst
set_location_assignment PIN_42 -to q_out[7]
set_location_assignment PIN_50 -to q_out[6]
set_location_assignment PIN_52 -to q_out[5]
set_location_assignment PIN_56 -to q_out[4]
set_location_assignment PIN_57 -to q_out[3]
set_location_assignment PIN_58 -to q_out[2]
set_location_assignment PIN_60 -to q_out[1]
set_location_assignment PIN_62 -to q_out[0]
set_global_assignment -name VECTOR_WAVEFORM_FILE signal.vwf
set_global_assignment -name SIGNALTAP_FILE signal.stp
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE signal.stp
set_location_assignment PIN_105 -to codekey[7]
set_location_assignment PIN_104 -to codekey[6]
set_location_assignment PIN_103 -to codekey[5]
set_location_assignment PIN_100 -to codekey[4]
set_location_assignment PIN_99 -to codekey[3]
set_location_assignment PIN_98 -to codekey[2]
set_location_assignment PIN_97 -to codekey[1]
set_location_assignment PIN_96 -to codekey[0]
set_location_assignment PIN_142 -to dataout[7]
set_location_assignment PIN_141 -to dataout[6]
set_location_assignment PIN_143 -to dataout[5]
set_location_assignment PIN_1 -to dataout[4]
set_location_assignment PIN_2 -to dataout[3]
set_location_assignment PIN_3 -to dataout[2]
set_location_assignment PIN_4 -to dataout[1]
set_location_assignment PIN_5 -to dataout[0]
set_location_assignment PIN_27 -to en[7]
set_location_assignment PIN_26 -to en[6]
set_location_assignment PIN_6 -to en[5]
set_location_assignment PIN_11 -to en[4]
set_location_assignment PIN_7 -to en[3]
set_location_assignment PIN_10 -to en[2]
set_location_assignment PIN_28 -to en[1]
set_location_assignment PIN_31 -to en[0]