signal.tan.rpt

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.

; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                      ; To                        ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------+---------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 139.80 MHz ( period = 7.153 ns )                    ; signal_gene:si|m[1]       ; signal_gene:si|address[0] ; clk        ; clk      ; None                        ; None                      ; 6.951 ns                ;
; N/A                                     ; 139.80 MHz ( period = 7.153 ns )                    ; signal_gene:si|m[1]       ; signal_gene:si|address[1] ; clk        ; clk      ; None                        ; None                      ; 6.951 ns                ;
; N/A                                     ; 139.80 MHz ( period = 7.153 ns )                    ; signal_gene:si|m[1]       ; signal_gene:si|address[2] ; clk        ; clk      ; None                        ; None                      ; 6.951 ns                ;
; N/A                                     ; 139.80 MHz ( period = 7.153 ns )                    ; signal_gene:si|m[1]       ; signal_gene:si|address[3] ; clk        ; clk      ; None                        ; None                      ; 6.951 ns                ;
; N/A                                     ; 139.80 MHz ( period = 7.153 ns )                    ; signal_gene:si|m[1]       ; signal_gene:si|address[4] ; clk        ; clk      ; None                        ; None                      ; 6.951 ns                ;
; N/A                                     ; 139.80 MHz ( period = 7.153 ns )                    ; signal_gene:si|m[1]       ; signal_gene:si|address[5] ; clk        ; clk      ; None                        ; None                      ; 6.951 ns                ;
; N/A                                     ; 139.80 MHz ( period = 7.153 ns )                    ; signal_gene:si|m[1]       ; signal_gene:si|address[6] ; clk        ; clk      ; None                        ; None                      ; 6.951 ns                ;
; N/A                                     ; 139.80 MHz ( period = 7.153 ns )                    ; signal_gene:si|m[1]       ; signal_gene:si|address[7] ; clk        ; clk      ; None                        ; None                      ; 6.951 ns                ;
; N/A                                     ; 139.80 MHz ( period = 7.153 ns )                    ; signal_gene:si|m[1]       ; signal_gene:si|address[8] ; clk        ; clk      ; None                        ; None                      ; 6.951 ns                ;
; N/A                                     ; 142.45 MHz ( period = 7.020 ns )                    ; signal_gene:si|m[0]       ; signal_gene:si|address[0] ; clk        ; clk      ; None                        ; None                      ; 6.818 ns                ;
; N/A                                     ; 142.45 MHz ( period = 7.020 ns )                    ; signal_gene:si|m[0]       ; signal_gene:si|address[1] ; clk        ; clk      ; None                        ; None                      ; 6.818 ns                ;
; N/A                                     ; 142.45 MHz ( period = 7.020 ns )                    ; signal_gene:si|m[0]       ; signal_gene:si|address[2] ; clk        ; clk      ; None                        ; None                      ; 6.818 ns                ;
; N/A                                     ; 142.45 MHz ( period = 7.020 ns )                    ; signal_gene:si|m[0]       ; signal_gene:si|address[3] ; clk        ; clk      ; None                        ; None                      ; 6.818 ns                ;
; N/A                                     ; 142.45 MHz ( period = 7.020 ns )                    ; signal_gene:si|m[0]       ; signal_gene:si|address[4] ; clk        ; clk      ; None                        ; None                      ; 6.818 ns                ;
; N/A                                     ; 142.45 MHz ( period = 7.020 ns )                    ; signal_gene:si|m[0]       ; signal_gene:si|address[5] ; clk        ; clk      ; None                        ; None                      ; 6.818 ns                ;
; N/A                                     ; 142.45 MHz ( period = 7.020 ns )                    ; signal_gene:si|m[0]       ; signal_gene:si|address[6] ; clk        ; clk      ; None                        ; None                      ; 6.818 ns                ;
; N/A                                     ; 142.45 MHz ( period = 7.020 ns )                    ; signal_gene:si|m[0]       ; signal_gene:si|address[7] ; clk        ; clk      ; None                        ; None                      ; 6.818 ns                ;
; N/A                                     ; 142.45 MHz ( period = 7.020 ns )                    ; signal_gene:si|m[0]       ; signal_gene:si|address[8] ; clk        ; clk      ; None                        ; None                      ; 6.818 ns                ;
; N/A                                     ; 144.45 MHz ( period = 6.923 ns )                    ; signal_gene:si|address[0] ; signal_gene:si|address[0] ; clk        ; clk      ; None                        ; None                      ; 6.721 ns                ;
; N/A                                     ; 144.45 MHz ( period = 6.923 ns )                    ; signal_gene:si|address[0] ; signal_gene:si|address[1] ; clk        ; clk      ; None                        ; None                      ; 6.721 ns                ;
; N/A                                     ; 144.45 MHz ( period = 6.923 ns )                    ; signal_gene:si|address[0] ; signal_gene:si|address[2] ; clk        ; clk      ; None                        ; None                      ; 6.721 ns                ;
; N/A                                     ; 144.45 MHz ( period = 6.923 ns )                    ; signal_gene:si|address[0] ; signal_gene:si|address[3] ; clk        ; clk      ; None                        ; None                      ; 6.721 ns                ;
; N/A                                     ; 144.45 MHz ( period = 6.923 ns )                    ; signal_gene:si|address[0] ; signal_gene:si|address[4] ; clk        ; clk      ; None                        ; None                      ; 6.721 ns                ;
; N/A                                     ; 144.45 MHz ( period = 6.923 ns )                    ; signal_gene:si|address[0] ; signal_gene:si|address[5] ; clk        ; clk      ; None                        ; None                      ; 6.721 ns                ;
; N/A                                     ; 144.45 MHz ( period = 6.923 ns )                    ; signal_gene:si|address[0] ; signal_gene:si|address[6] ; clk        ; clk      ; None                        ; None                      ; 6.721 ns                ;
; N/A                                     ; 144.45 MHz ( period = 6.923 ns )                    ; signal_gene:si|address[0] ; signal_gene:si|address[7] ; clk        ; clk      ; None                        ; None                      ; 6.721 ns                ;
; N/A                                     ; 144.45 MHz ( period = 6.923 ns )                    ; signal_gene:si|address[0] ; signal_gene:si|address[8] ; clk        ; clk      ; None                        ; None                      ; 6.721 ns                ;
; N/A                                     ; 147.43 MHz ( period = 6.783 ns )                    ; signal_gene:si|m[2]       ; signal_gene:si|address[0] ; clk        ; clk      ; None                        ; None                      ; 6.581 ns                ;
; N/A                                     ; 147.43 MHz ( period = 6.783 ns )                    ; signal_gene:si|m[2]       ; signal_gene:si|address[1] ; clk        ; clk      ; None                        ; None                      ; 6.581 ns                ;
; N/A                                     ; 147.43 MHz ( period = 6.783 ns )                    ; signal_gene:si|m[2]       ; signal_gene:si|address[2] ; clk        ; clk      ; None                        ; None                      ; 6.581 ns                ;
; N/A                                     ; 147.43 MHz ( period = 6.783 ns )                    ; signal_gene:si|m[2]       ; signal_gene:si|address[3] ; clk        ; clk      ; None                        ; None                      ; 6.581 ns                ;
; N/A                                     ; 147.43 MHz ( period = 6.783 ns )                    ; signal_gene:si|m[2]       ; signal_gene:si|address[4] ; clk        ; clk      ; None                        ; None                      ; 6.581 ns                ;
; N/A                                     ; 147.43 MHz ( period = 6.783 ns )                    ; signal_gene:si|m[2]       ; signal_gene:si|address[5] ; clk        ; clk      ; None                        ; None                      ; 6.581 ns                ;
; N/A                                     ; 147.43 MHz ( period = 6.783 ns )                    ; signal_gene:si|m[2]       ; signal_gene:si|address[6] ; clk        ; clk      ; None                        ; None                      ; 6.581 ns                ;