signal.tan.summary

yong VerilogHDL yu yan bianxie de pinlv fa sheng qi,shi yong ISE ruan jian da kai.

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 18.132 ns
From           : codekey[5]
To             : signal_gene:si|k[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 13.693 ns
From           : key:ke|en[5]
To             : dataout[2]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 13.994 ns
From           : codekey[6]
To             : dataout[2]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.445 ns
From           : codekey[0]
To             : signal_gene:si|address[7]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 139.80 MHz ( period = 7.153 ns )
From           : signal_gene:si|m[1]
To             : signal_gene:si|address[8]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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