dds.sta.rpt

来自「dds算法的fpga实现 altera 根据不同设置」· RPT 代码 · 共 488 行 · 第 1/4 页

------------------------------
; Fast Model Removal Summary ;
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No paths to report.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width                                                                                                                                                       ;
+--------+--------------+----------------+--------+-------+------------+---------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Pulse  ; Clock ; Clock Edge ; Target                                                                                                        ;
+--------+--------------+----------------+--------+-------+------------+---------------------------------------------------------------------------------------------------------------+
; -1.000 ; 1.000        ; 2.000          ; Period ; clk   ; Rise       ; clk                                                                                                           ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[0]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[0]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[1]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[1]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[2]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[2]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[3]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[3]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg0 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg0 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg1 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg1 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg2 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg2 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg3 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg3 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg4 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg4 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg5 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg5 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg6 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg6 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg7 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg7 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg8 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg8 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg9 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg9 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[8]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[8]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[9]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[9]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[10]                         ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[10]                         ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[11]                         ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[11]                         ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg0 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg0 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg1 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg1 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg2 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg2 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg3 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg3 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg4 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg4 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[4]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[4]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[5]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[5]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[6]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[6]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[7]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[7]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg0 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg0 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg1 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg1 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg2 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg2 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg3 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg3 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg4 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg4 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg5 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg5 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg6 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg6 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg7 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg7 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[0]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[0]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[1]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[1]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[2]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[2]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[4]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[4]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[5]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[5]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[6]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[6]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[7]                          ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[7]                          ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg0 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg0 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg1 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg1 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg2 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg2 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg3 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg3 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg4 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg4 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg5 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg5 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg6 ;
; -0.417 ; 0.500        ; 0.917          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg6 ;
; -0.417 ; 0.500        ; 0.917          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg7 ;
+--------+--------------+----------------+--------+-------+------------+---------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------+
; Setup Transfers                                                   ;
+------------+----------+----------+----------+----------+----------+
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+----------+----------+----------+----------+----------+
; clk        ; clk      ; 1488     ; 0        ; 0        ; 0        ;
+------------+----------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.