dds.sta.rpt

来自「dds算法的fpga实现 altera 根据不同设置」· RPT 代码 · 共 488 行 · 第 1/4 页

; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[2]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[2]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[3]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[3]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg0 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg0 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg1 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg1 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg2 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg2 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg3 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg3 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg4 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg4 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg5 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg5 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg6 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg6 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg7 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg7 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg8 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg8 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg9 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a0~porta_address_reg9 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[8]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[8]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[9]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[9]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[10]                         ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[10]                         ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[11]                         ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[11]                         ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg0 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg0 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg1 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg1 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg2 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg2 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg3 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg3 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg4 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a8~porta_address_reg4 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[4]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[4]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[5]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[5]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[6]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[6]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[7]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[7]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg0 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg0 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg1 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg1 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg2 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg2 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg3 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg3 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg4 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg4 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg5 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg5 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg6 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg6 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg7 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|ram_block1a4~porta_address_reg7 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[0]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[0]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[1]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[1]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[2]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_cose:cose1|altsyncram:altsyncram_component|altsyncram_2571:auto_generated|q_a[2]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[4]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[4]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[5]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[5]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[6]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[6]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[7]                          ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|q_a[7]                          ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg0 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg0 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg1 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg1 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg2 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg2 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg3 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg3 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg4 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg4 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg5 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg5 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg6 ;
; -0.815 ; 0.500        ; 1.315          ; Low    ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg6 ;
; -0.815 ; 0.500        ; 1.315          ; High   ; clk   ; Rise       ; rom_sine:sine1|altsyncram:altsyncram_component|altsyncram_7571:auto_generated|ram_block1a4~porta_address_reg7 ;
+--------+--------------+----------------+--------+-------+------------+---------------------------------------------------------------------------------------------------------------+


+--------------------------------+
; Fast Model Setup Summary       ;
+-------+--------+---------------+
; Clock ; Slack  ; End Point TNS ;
+-------+--------+---------------+
; clk   ; -0.558 ; -10.430       ;
+-------+--------+---------------+


+-------------------------------+
; Fast Model Hold Summary       ;
+-------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+-------+-------+---------------+
; clk   ; 0.365 ; 0.000         ;
+-------+-------+---------------+


-------------------------------
; Fast Model Recovery Summary ;
-------------------------------
No paths to report.