_primary.vhd

来自「基于altera系列芯片lvds接口的fpga设计 verilog源码」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity stratix_mac_register is
    generic(
        data_width      : integer := 18
    );
    port(
        data            : in     vl_logic_vector(71 downto 0);
        clk             : in     vl_logic;
        aclr            : in     vl_logic;
        ena             : in     vl_logic;
        dataout         : out    vl_logic_vector(71 downto 0);
        async           : in     vl_logic
    );
end stratix_mac_register;