decode.txt

基于VHDL语言的循环码编码器的程序

library ieee;
use ieee.std_logic_1164.all;
entity crc_156 is
port ( clk,m: in std_logic;
f: out std_logic) ;
end crc_156;
architecture rtl of crc_156 is
  signal d: std_logic_vector (1 to 9) ;
begin
 process (clk)
  variable c: integer range 1 to 15;
  variable e: std_logic;
  begin
    if ( clk'event) and ( clk = '1') then
if ( c <= 6) then
f <= m;
e:= m xor d (9) ;
else
f <= d (9) ;
e := '0';
end if;
d (9) <= d (8) ;
d (6) <= e xor d (5) ;
d (5) <= e xor d (4) ;
d (4) <= e xor d (3) ;
d (1) <= e;
c:= c + 1;
end if;
    end process;
  end rtl;