lpf.vhd

来自「全数字fsk调制解调的实现 verilog源码」· VHDL 代码 · 共 38 行

--------该模块实现低通滤波--------
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity lpf is
port (clk    :in  std_logic; 
      din    :in  std_logic;  
      dout   :out std_logic);      
end lpf;

architecture behav of lpf is

signal p   :std_logic_vector(16 downto 0);

begin

process(clk)
variable add :integer range 0 to 31 ;
begin
if clk'event and clk='1' then 
p(16 downto 1)<=p(15 downto 0);
p(0)<=din;
add:= conv_integer(p(0))+conv_integer(p(1))+conv_integer(p(2))+conv_integer(p(3))  --change to "integer"
      +conv_integer(p(4))+conv_integer(p(5))+conv_integer(p(6))+conv_integer(p(7))
       +conv_integer(p(8))+conv_integer(p(9))+conv_integer(p(10))+conv_integer(p(11))
       +conv_integer(p(12))+conv_integer(p(13))+conv_integer(p(14))+conv_integer(p(15))+conv_integer(p(16)); --做相关运算
if add<17 then dout<='0'; else dout<='1';
 end if;    --滤波                
end if ;                 
end process;

end architecture behav;