2fsk_final.tan.qmsg

全数字fsk调制解调的实现 verilog源码

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "Quartus II" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "Quartus II" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "2fsk_final.bdf" "" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { -40 -288 -120 -24 "clk" "" } } } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "Quartus II" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "Quartus II" 0}