📄 prev_cmp_2fsk_final.tan.qmsg
字号:
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "lpf:inst3\|dout pj:inst7\|dout clk 2.4 ns " "Info: Found hold time violation between source pin or register \"lpf:inst3\|dout\" and destination pin or register \"pj:inst7\|dout\" for clock \"clk\" (Hold time is 2.4 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.500 ns + Largest " "Info: + Largest clock skew is 4.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 14.200 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 14.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 6; CLK Node = 'clk'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "2fsk_final.bdf" "" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { -40 -288 -120 -24 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns div64:inst11\|divout 2 REG LC1_C24 17 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_C24; Fanout = 17; REG Node = 'div64:inst11\|divout'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { clk div64:inst11|divout } "NODE_NAME" } } { "div64.vhd" "" { Text "E:/quartus/program/2fsk_final/div64.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.500 ns) 6.300 ns div8:inst\|divout 3 REG LC6_E3 25 " "Info: 3: + IC(2.900 ns) + CELL(0.500 ns) = 6.300 ns; Loc. = LC6_E3; Fanout = 25; REG Node = 'div8:inst\|divout'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { div64:inst11|divout div8:inst|divout } "NODE_NAME" } } { "div8.vhd" "" { Text "E:/quartus/program/2fsk_final/div8.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.500 ns) 8.800 ns div128:inst14\|divout 4 REG LC8_B10 11 " "Info: 4: + IC(2.000 ns) + CELL(0.500 ns) = 8.800 ns; Loc. = LC8_B10; Fanout = 11; REG Node = 'div128:inst14\|divout'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { div8:inst|divout div128:inst14|divout } "NODE_NAME" } } { "div128.vhd" "" { Text "E:/quartus/program/2fsk_final/div128.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.500 ns) 12.100 ns dpll:inst1\|bsyn 5 REG LC3_A36 2 " "Info: 5: + IC(2.800 ns) + CELL(0.500 ns) = 12.100 ns; Loc. = LC3_A36; Fanout = 2; REG Node = 'dpll:inst1\|bsyn'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.300 ns" { div128:inst14|divout dpll:inst1|bsyn } "NODE_NAME" } } { "dpll.vhd" "" { Text "E:/quartus/program/2fsk_final/dpll.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.000 ns) 14.200 ns pj:inst7\|dout 6 REG LC6_C32 1 " "Info: 6: + IC(2.100 ns) + CELL(0.000 ns) = 14.200 ns; Loc. = LC6_C32; Fanout = 1; REG Node = 'pj:inst7\|dout'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { dpll:inst1|bsyn pj:inst7|dout } "NODE_NAME" } } { "pj.vhd" "" { Text "E:/quartus/program/2fsk_final/pj.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns ( 28.17 % ) " "Info: Total cell delay = 4.000 ns ( 28.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.200 ns ( 71.83 % ) " "Info: Total interconnect delay = 10.200 ns ( 71.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Quartus II" 0} } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "14.200 ns" { clk div64:inst11|divout div8:inst|divout div128:inst14|divout dpll:inst1|bsyn pj:inst7|dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "14.200 ns" { clk {} clk~out {} div64:inst11|divout {} div8:inst|divout {} div128:inst14|divout {} dpll:inst1|bsyn {} pj:inst7|dout {} } { 0.000ns 0.000ns 0.400ns 2.900ns 2.000ns 2.800ns 2.100ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.500ns 0.500ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.700 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 9.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 6; CLK Node = 'clk'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "2fsk_final.bdf" "" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { -40 -288 -120 -24 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns div64:inst11\|divout 2 REG LC1_C24 17 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_C24; Fanout = 17; REG Node = 'div64:inst11\|divout'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { clk div64:inst11|divout } "NODE_NAME" } } { "div64.vhd" "" { Text "E:/quartus/program/2fsk_final/div64.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.500 ns) 6.300 ns div64:inst17\|divout 3 REG LC1_E3 41 " "Info: 3: + IC(2.900 ns) + CELL(0.500 ns) = 6.300 ns; Loc. = LC1_E3; Fanout = 41; REG Node = 'div64:inst17\|divout'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { div64:inst11|divout div64:inst17|divout } "NODE_NAME" } } { "div64.vhd" "" { Text "E:/quartus/program/2fsk_final/div64.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(0.000 ns) 9.700 ns lpf:inst3\|dout 4 REG LC1_A36 3 " "Info: 4: + IC(3.400 ns) + CELL(0.000 ns) = 9.700 ns; Loc. = LC1_A36; Fanout = 3; REG Node = 'lpf:inst3\|dout'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { div64:inst17|divout lpf:inst3|dout } "NODE_NAME" } } { "lpf.vhd" "" { Text "E:/quartus/program/2fsk_final/lpf.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 30.93 % ) " "Info: Total cell delay = 3.000 ns ( 30.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.700 ns ( 69.07 % ) " "Info: Total interconnect delay = 6.700 ns ( 69.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Quartus II" 0} } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "9.700 ns" { clk div64:inst11|divout div64:inst17|divout lpf:inst3|dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "9.700 ns" { clk {} clk~out {} div64:inst11|divout {} div64:inst17|divout {} lpf:inst3|dout {} } { 0.000ns 0.000ns 0.400ns 2.900ns 3.400ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Quartus II" 0} } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "14.200 ns" { clk div64:inst11|divout div8:inst|divout div128:inst14|divout dpll:inst1|bsyn pj:inst7|dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "14.200 ns" { clk {} clk~out {} div64:inst11|divout {} div8:inst|divout {} div128:inst14|divout {} dpll:inst1|bsyn {} pj:inst7|dout {} } { 0.000ns 0.000ns 0.400ns 2.900ns 2.000ns 2.800ns 2.100ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.500ns 0.500ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "9.700 ns" { clk div64:inst11|divout div64:inst17|divout lpf:inst3|dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "9.700 ns" { clk {} clk~out {} div64:inst11|divout {} div64:inst17|divout {} lpf:inst3|dout {} } { 0.000ns 0.000ns 0.400ns 2.900ns 3.400ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns - " "Info: - Micro clock to output delay of source is 0.500 ns" { } { { "lpf.vhd" "" { Text "E:/quartus/program/2fsk_final/lpf.vhd" 11 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.900 ns - Shortest register register " "Info: - Shortest register to register delay is 2.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpf:inst3\|dout 1 REG LC1_A36 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A36; Fanout = 3; REG Node = 'lpf:inst3\|dout'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpf:inst3|dout } "NODE_NAME" } } { "lpf.vhd" "" { Text "E:/quartus/program/2fsk_final/lpf.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.800 ns) 2.900 ns pj:inst7\|dout 2 REG LC6_C32 1 " "Info: 2: + IC(2.100 ns) + CELL(0.800 ns) = 2.900 ns; Loc. = LC6_C32; Fanout = 1; REG Node = 'pj:inst7\|dout'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { lpf:inst3|dout pj:inst7|dout } "NODE_NAME" } } { "pj.vhd" "" { Text "E:/quartus/program/2fsk_final/pj.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.800 ns ( 27.59 % ) " "Info: Total cell delay = 0.800 ns ( 27.59 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.100 ns ( 72.41 % ) " "Info: Total interconnect delay = 2.100 ns ( 72.41 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Quartus II" 0} } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { lpf:inst3|dout pj:inst7|dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.900 ns" { lpf:inst3|dout {} pj:inst7|dout {} } { 0.000ns 2.100ns } { 0.000ns 0.800ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" { } { { "pj.vhd" "" { Text "E:/quartus/program/2fsk_final/pj.vhd" 7 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "Quartus II" 0} } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "14.200 ns" { clk div64:inst11|divout div8:inst|divout div128:inst14|divout dpll:inst1|bsyn pj:inst7|dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "14.200 ns" { clk {} clk~out {} div64:inst11|divout {} div8:inst|divout {} div128:inst14|divout {} dpll:inst1|bsyn {} pj:inst7|dout {} } { 0.000ns 0.000ns 0.400ns 2.900ns 2.000ns 2.800ns 2.100ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.500ns 0.500ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "9.700 ns" { clk div64:inst11|divout div64:inst17|divout lpf:inst3|dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "9.700 ns" { clk {} clk~out {} div64:inst11|divout {} div64:inst17|divout {} lpf:inst3|dout {} } { 0.000ns 0.000ns 0.400ns 2.900ns 3.400ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { lpf:inst3|dout pj:inst7|dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "2.900 ns" { lpf:inst3|dout {} pj:inst7|dout {} } { 0.000ns 2.100ns } { 0.000ns 0.800ns } "" } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "Quartus II" 0}
{ "Info" "ITDB_TSU_RESULT" "mx_7821:inst6\|dout\[7\] din\[7\] clk 1.600 ns register " "Info: tsu for register \"mx_7821:inst6\|dout\[7\]\" (data pin = \"din\[7\]\", clock pin = \"clk\") is 1.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.700 ns + Longest pin register " "Info: + Longest pin to register delay is 6.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns din\[7\] 1 PIN PIN_102 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_102; Fanout = 1; PIN Node = 'din\[7\]'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { din[7] } "NODE_NAME" } } { "2fsk_final.bdf" "" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { 504 -120 48 520 "din\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.800 ns) 6.700 ns mx_7821:inst6\|dout\[7\] 2 REG LC7_A1 2 " "Info: 2: + IC(1.000 ns) + CELL(0.800 ns) = 6.700 ns; Loc. = LC7_A1; Fanout = 2; REG Node = 'mx_7821:inst6\|dout\[7\]'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { din[7] mx_7821:inst6|dout[7] } "NODE_NAME" } } { "mx_7821.vhd" "" { Text "E:/quartus/program/2fsk_final/mx_7821.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns ( 85.07 % ) " "Info: Total cell delay = 5.700 ns ( 85.07 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns ( 14.93 % ) " "Info: Total interconnect delay = 1.000 ns ( 14.93 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Quartus II" 0} } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "6.700 ns" { din[7] mx_7821:inst6|dout[7] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "6.700 ns" { din[7] {} din[7]~out {} mx_7821:inst6|dout[7] {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 4.900ns 0.800ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "mx_7821.vhd" "" { Text "E:/quartus/program/2fsk_final/mx_7821.vhd" 28 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.700 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 6; CLK Node = 'clk'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "2fsk_final.bdf" "" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { -40 -288 -120 -24 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns div64:inst11\|divout 2 REG LC1_C24 17 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_C24; Fanout = 17; REG Node = 'div64:inst11\|divout'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { clk div64:inst11|divout } "NODE_NAME" } } { "div64.vhd" "" { Text "E:/quartus/program/2fsk_final/div64.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.800 ns) + CELL(0.000 ns) 5.700 ns mx_7821:inst6\|dout\[7\] 3 REG LC7_A1 2 " "Info: 3: + IC(2.800 ns) + CELL(0.000 ns) = 5.700 ns; Loc. = LC7_A1; Fanout = 2; REG Node = 'mx_7821:inst6\|dout\[7\]'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { div64:inst11|divout mx_7821:inst6|dout[7] } "NODE_NAME" } } { "mx_7821.vhd" "" { Text "E:/quartus/program/2fsk_final/mx_7821.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns ( 43.86 % ) " "Info: Total cell delay = 2.500 ns ( 43.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns ( 56.14 % ) " "Info: Total interconnect delay = 3.200 ns ( 56.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Quartus II" 0} } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { clk div64:inst11|divout mx_7821:inst6|dout[7] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.700 ns" { clk {} clk~out {} div64:inst11|divout {} mx_7821:inst6|dout[7] {} } { 0.000ns 0.000ns 0.400ns 2.800ns } { 0.000ns 2.000ns 0.500ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Quartus II" 0} } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "6.700 ns" { din[7] mx_7821:inst6|dout[7] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "6.700 ns" { din[7] {} din[7]~out {} mx_7821:inst6|dout[7] {} } { 0.000ns 0.000ns 1.000ns } { 0.000ns 4.900ns 0.800ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { clk div64:inst11|divout mx_7821:inst6|dout[7] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.700 ns" { clk {} clk~out {} div64:inst11|divout {} mx_7821:inst6|dout[7] {} } { 0.000ns 0.000ns 0.400ns 2.800ns } { 0.000ns 2.000ns 0.500ns 0.000ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "Quartus II" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk fsk\[6\] f2_zb:inst19\|rom16_1:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~reg_ra0 28.600 ns memory " "Info: tco from clock \"clk\" to destination pin \"fsk\[6\]\" through memory \"f2_zb:inst19\|rom16_1:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~reg_ra0\" is 28.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.400 ns + Longest memory " "Info: + Longest clock path from clock \"clk\" to source memory is 11.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 6; CLK Node = 'clk'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "2fsk_final.bdf" "" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { -40 -288 -120 -24 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns div64:inst11\|divout 2 REG LC1_C24 17 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_C24; Fanout = 17; REG Node = 'div64:inst11\|divout'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { clk div64:inst11|divout } "NODE_NAME" } } { "div64.vhd" "" { Text "E:/quartus/program/2fsk_final/div64.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.500 ns) 6.300 ns div8:inst\|divout 3 REG LC6_E3 25 " "Info: 3: + IC(2.900 ns) + CELL(0.500 ns) = 6.300 ns; Loc. = LC6_E3; Fanout = 25; REG Node = 'div8:inst\|divout'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { div64:inst11|divout div8:inst|divout } "NODE_NAME" } } { "div8.vhd" "" { Text "E:/quartus/program/2fsk_final/div8.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(0.500 ns) 8.900 ns div16:inst13\|divout 4 REG LC8_C13 36 " "Info: 4: + IC(2.100 ns) + CELL(0.500 ns) = 8.900 ns; Loc. = LC8_C13; Fanout = 36; REG Node = 'div16:inst13\|divout'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.600 ns" { div8:inst|divout div16:inst13|divout } "NODE_NAME" } } { "div16.vhd" "" { Text "E:/quartus/program/2fsk_final/div16.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 11.400 ns f2_zb:inst19\|rom16_1:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~reg_ra0 5 MEM EC11_F 1 " "Info: 5: + IC(2.500 ns) + CELL(0.000 ns) = 11.400 ns; Loc. = EC11_F; Fanout = 1; MEM Node = 'f2_zb:inst19\|rom16_1:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~reg_ra0'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { div16:inst13|divout f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "e:/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns ( 30.70 % ) " "Info: Total cell delay = 3.500 ns ( 30.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.900 ns ( 69.30 % ) " "Info: Total interconnect delay = 7.900 ns ( 69.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Quartus II" 0} } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "11.400 ns" { clk div64:inst11|divout div8:inst|divout div16:inst13|divout f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "11.400 ns" { clk {} clk~out {} div64:inst11|divout {} div8:inst|divout {} div16:inst13|divout {} f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 {} } { 0.000ns 0.000ns 0.400ns 2.900ns 2.100ns 2.500ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.500ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" { } { { "altrom.tdf" "" { Text "e:/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.800 ns + Longest memory pin " "Info: + Longest memory to pin delay is 16.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns f2_zb:inst19\|rom16_1:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~reg_ra0 1 MEM EC11_F 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = EC11_F; Fanout = 1; MEM Node = 'f2_zb:inst19\|rom16_1:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~reg_ra0'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "e:/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.400 ns) 4.400 ns f2_zb:inst19\|rom16_1:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~mem_cell_ra0 2 MEM EC11_F 1 " "Info: 2: + IC(0.000 ns) + CELL(4.400 ns) = 4.400 ns; Loc. = EC11_F; Fanout = 1; MEM Node = 'f2_zb:inst19\|rom16_1:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]~mem_cell_ra0'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~mem_cell_ra0 } "NODE_NAME" } } { "altrom.tdf" "" { Text "e:/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 5.800 ns f2_zb:inst19\|rom16_1:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\] 3 MEM EC11_F 1 " "Info: 3: + IC(0.000 ns) + CELL(1.400 ns) = 5.800 ns; Loc. = EC11_F; Fanout = 1; MEM Node = 'f2_zb:inst19\|rom16_1:u1\|lpm_rom:lpm_rom_component\|altrom:srom\|q\[6\]'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~mem_cell_ra0 f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6] } "NODE_NAME" } } { "altrom.tdf" "" { Text "e:/quartus/libraries/megafunctions/altrom.tdf" 82 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.600 ns) 9.700 ns mux:inst5\|dout\[6\]~33 4 COMB LC1_C15 1 " "Info: 4: + IC(2.300 ns) + CELL(1.600 ns) = 9.700 ns; Loc. = LC1_C15; Fanout = 1; COMB Node = 'mux:inst5\|dout\[6\]~33'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6] mux:inst5|dout[6]~33 } "NODE_NAME" } } { "mux.vhd" "" { Text "E:/quartus/program/2fsk_final/mux.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(6.300 ns) 16.800 ns fsk\[6\] 5 PIN PIN_60 0 " "Info: 5: + IC(0.800 ns) + CELL(6.300 ns) = 16.800 ns; Loc. = PIN_60; Fanout = 0; PIN Node = 'fsk\[6\]'" { } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "7.100 ns" { mux:inst5|dout[6]~33 fsk[6] } "NODE_NAME" } } { "2fsk_final.bdf" "" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { -48 688 864 -32 "fsk\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.700 ns ( 81.55 % ) " "Info: Total cell delay = 13.700 ns ( 81.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.100 ns ( 18.45 % ) " "Info: Total interconnect delay = 3.100 ns ( 18.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Quartus II" 0} } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "16.800 ns" { f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~mem_cell_ra0 f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6] mux:inst5|dout[6]~33 fsk[6] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "16.800 ns" { f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 {} f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~mem_cell_ra0 {} f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6] {} mux:inst5|dout[6]~33 {} fsk[6] {} } { 0.000ns 0.000ns 0.000ns 2.300ns 0.800ns } { 0.000ns 4.400ns 1.400ns 1.600ns 6.300ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Quartus II" 0} } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "11.400 ns" { clk div64:inst11|divout div8:inst|divout div16:inst13|divout f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "11.400 ns" { clk {} clk~out {} div64:inst11|divout {} div8:inst|divout {} div16:inst13|divout {} f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 {} } { 0.000ns 0.000ns 0.400ns 2.900ns 2.100ns 2.500ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.500ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "16.800 ns" { f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~mem_cell_ra0 f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6] mux:inst5|dout[6]~33 fsk[6] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "16.800 ns" { f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~reg_ra0 {} f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]~mem_cell_ra0 {} f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6] {} mux:inst5|dout[6]~33 {} fsk[6] {} } { 0.000ns 0.000ns 0.000ns 2.300ns 0.800ns } { 0.000ns 4.400ns 1.400ns 1.600ns 6.300ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "Quartus II" 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -