prev_cmp_2fsk_final.tan.qmsg

全数字fsk调制解调的实现 verilog源码

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "8 " "Warning: Found 8 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div16:inst13\|divout " "Info: Detected ripple clock \"div16:inst13\|divout\" as buffer" {  } { { "div16.vhd" "" { Text "E:/quartus/program/2fsk_final/div16.vhd" 11 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "div16:inst13\|divout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "Quartus II" 0} { "Info" "ITAN_RIPPLE_CLK" "div8:inst\|divout " "Info: Detected ripple clock \"div8:inst\|divout\" as buffer" {  } { { "div8.vhd" "" { Text "E:/quartus/program/2fsk_final/div8.vhd" 11 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "div8:inst\|divout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "Quartus II" 0} { "Info" "ITAN_RIPPLE_CLK" "div8:inst16\|divout " "Info: Detected ripple clock \"div8:inst16\|divout\" as buffer" {  } { { "div8.vhd" "" { Text "E:/quartus/program/2fsk_final/div8.vhd" 11 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "div8:inst16\|divout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "Quartus II" 0} { "Info" "ITAN_RIPPLE_CLK" "div64:inst17\|divout " "Info: Detected ripple clock \"div64:inst17\|divout\" as buffer" {  } { { "div64.vhd" "" { Text "E:/quartus/program/2fsk_final/div64.vhd" 11 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "div64:inst17\|divout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "Quartus II" 0} { "Info" "ITAN_RIPPLE_CLK" "div128:inst14\|divout " "Info: Detected ripple clock \"div128:inst14\|divout\" as buffer" {  } { { "div128.vhd" "" { Text "E:/quartus/program/2fsk_final/div128.vhd" 11 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "div128:inst14\|divout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "Quartus II" 0} { "Info" "ITAN_RIPPLE_CLK" "dpll:inst1\|bsyn " "Info: Detected ripple clock \"dpll:inst1\|bsyn\" as buffer" {  } { { "dpll.vhd" "" { Text "E:/quartus/program/2fsk_final/dpll.vhd" 12 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "dpll:inst1\|bsyn" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "Quartus II" 0} { "Info" "ITAN_RIPPLE_CLK" "div1024:inst15\|divout " "Info: Detected ripple clock \"div1024:inst15\|divout\" as buffer" {  } { { "div1024.vhd" "" { Text "E:/quartus/program/2fsk_final/div1024.vhd" 11 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "div1024:inst15\|divout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "Quartus II" 0} { "Info" "ITAN_RIPPLE_CLK" "div64:inst11\|divout " "Info: Detected ripple clock \"div64:inst11\|divout\" as buffer" {  } { { "div64.vhd" "" { Text "E:/quartus/program/2fsk_final/div64.vhd" 11 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "div64:inst11\|divout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "Quartus II" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "Quartus II" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpf:inst3\|p\[2\] register lpf:inst3\|dout 34.01 MHz 29.4 ns Internal " "Info: Clock \"clk\" has Internal fmax of 34.01 MHz between source register \"lpf:inst3\|p\[2\]\" and destination register \"lpf:inst3\|dout\" (period= 29.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "28.300 ns + Longest register register " "Info: + Longest register to register delay is 28.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpf:inst3\|p\[2\] 1 REG LC5_A29 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_A29; Fanout = 3; REG Node = 'lpf:inst3\|p\[2\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpf:inst3|p[2] } "NODE_NAME" } } { "lpf.vhd" "" { Text "E:/quartus/program/2fsk_final/lpf.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 1.900 ns lpf:inst3\|Add1~77 2 COMB LC2_A29 3 " "Info: 2: + IC(0.300 ns) + CELL(1.600 ns) = 1.900 ns; Loc. = LC2_A29; Fanout = 3; COMB Node = 'lpf:inst3\|Add1~77'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { lpf:inst3|p[2] lpf:inst3|Add1~77 } "NODE_NAME" } } { "lpf.vhd" "" { Text "E:/quartus/program/2fsk_final/lpf.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 3.600 ns lpf:inst3\|Add2~350 3 COMB LC1_A29 2 " "Info: 3: + IC(0.300 ns) + CELL(1.400 ns) = 3.600 ns; Loc. = LC1_A29; Fanout = 2; COMB Node = 'lpf:inst3\|Add2~350'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { lpf:inst3|Add1~77 lpf:inst3|Add2~350 } "NODE_NAME" } } { "lpf.vhd" "" { Text "E:/quartus/program/2fsk_final/lpf.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 6.200 ns lpf:inst3\|lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\] 4 COMB LC3_A30 2 " "Info: 4: + IC(1.000 ns) + CELL(1.600 ns) = 6.200 ns; Loc. = LC3_A30; Fanout = 2; COMB Node = 'lpf:inst3\|lpm_add_sub:Add3\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.600 ns" { lpf:inst3|Add2~350 lpf:inst3|lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 8.800 ns lpf:inst3\|lpm_add_sub:Add6\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\] 5 COMB LC2_A32 2 " "Info: 5: + IC(1.000 ns) + CELL(1.600 ns) = 8.800 ns; Loc. = LC2_A32; Fanout = 2; COMB Node = 'lpf:inst3\|lpm_add_sub:Add6\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.600 ns" { lpf:inst3|lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] lpf:inst3|lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 11.400 ns lpf:inst3\|lpm_add_sub:Add7\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\]~55 6 COMB LC1_A31 2 " "Info: 6: + IC(1.000 ns) + CELL(1.600 ns) = 11.400 ns; Loc. = LC1_A31; Fanout = 2; COMB Node = 'lpf:inst3\|lpm_add_sub:Add7\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\]~55'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.600 ns" { lpf:inst3|lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~55 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 13.800 ns lpf:inst3\|lpm_add_sub:Add7\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~47 7 COMB LC8_A32 2 " "Info: 7: + IC(1.000 ns) + CELL(1.400 ns) = 13.800 ns; Loc. = LC8_A32; Fanout = 2; COMB Node = 'lpf:inst3\|lpm_add_sub:Add7\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[2\]~47'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~55 lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~47 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 15.500 ns lpf:inst3\|lpm_add_sub:Add7\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~41 8 COMB LC6_A32 1 " "Info: 8: + IC(0.300 ns) + CELL(1.400 ns) = 15.500 ns; Loc. = LC6_A32; Fanout = 1; COMB Node = 'lpf:inst3\|lpm_add_sub:Add7\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[3\]~41'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~47 lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~41 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.400 ns) 17.200 ns lpf:inst3\|lpm_add_sub:Add7\|addcore:adder\|unreg_res_node\[4\] 9 COMB LC5_A32 1 " "Info: 9: + IC(0.300 ns) + CELL(1.400 ns) = 17.200 ns; Loc. = LC5_A32; Fanout = 1; COMB Node = 'lpf:inst3\|lpm_add_sub:Add7\|addcore:adder\|unreg_res_node\[4\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~41 lpf:inst3|lpm_add_sub:Add7|addcore:adder|unreg_res_node[4] } "NODE_NAME" } } { "addcore.tdf" "" { Text "e:/quartus/libraries/megafunctions/addcore.tdf" 98 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 19.600 ns lpf:inst3\|lpm_add_sub:Add8\|addcore:adder\|unreg_res_node\[4\] 10 COMB LC7_A33 1 " "Info: 10: + IC(1.000 ns) + CELL(1.400 ns) = 19.600 ns; Loc. = LC7_A33; Fanout = 1; COMB Node = 'lpf:inst3\|lpm_add_sub:Add8\|addcore:adder\|unreg_res_node\[4\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { lpf:inst3|lpm_add_sub:Add7|addcore:adder|unreg_res_node[4] lpf:inst3|lpm_add_sub:Add8|addcore:adder|unreg_res_node[4] } "NODE_NAME" } } { "addcore.tdf" "" { Text "e:/quartus/libraries/megafunctions/addcore.tdf" 98 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.400 ns) 22.000 ns lpf:inst3\|lpm_add_sub:Add9\|addcore:adder\|unreg_res_node\[4\] 11 COMB LC8_A35 2 " "Info: 11: + IC(1.000 ns) + CELL(1.400 ns) = 22.000 ns; Loc. = LC8_A35; Fanout = 2; COMB Node = 'lpf:inst3\|lpm_add_sub:Add9\|addcore:adder\|unreg_res_node\[4\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { lpf:inst3|lpm_add_sub:Add8|addcore:adder|unreg_res_node[4] lpf:inst3|lpm_add_sub:Add9|addcore:adder|unreg_res_node[4] } "NODE_NAME" } } { "addcore.tdf" "" { Text "e:/quartus/libraries/megafunctions/addcore.tdf" 98 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.600 ns) 24.600 ns lpf:inst3\|lpm_add_sub:Add14\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[4\] 12 COMB LC8_A34 1 " "Info: 12: + IC(1.000 ns) + CELL(1.600 ns) = 24.600 ns; Loc. = LC8_A34; Fanout = 1; COMB Node = 'lpf:inst3\|lpm_add_sub:Add14\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[4\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.600 ns" { lpf:inst3|lpm_add_sub:Add9|addcore:adder|unreg_res_node[4] lpf:inst3|lpm_add_sub:Add14|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 26.600 ns lpf:inst3\|lpm_add_sub:Add14\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\]~85 13 COMB LC1_A34 1 " "Info: 13: + IC(0.300 ns) + CELL(1.700 ns) = 26.600 ns; Loc. = LC1_A34; Fanout = 1; COMB Node = 'lpf:inst3\|lpm_add_sub:Add14\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[1\]~85'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { lpf:inst3|lpm_add_sub:Add14|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] lpf:inst3|lpm_add_sub:Add14|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~85 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "e:/quartus/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(0.800 ns) 28.300 ns lpf:inst3\|dout 14 REG LC1_A36 3 " "Info: 14: + IC(0.900 ns) + CELL(0.800 ns) = 28.300 ns; Loc. = LC1_A36; Fanout = 3; REG Node = 'lpf:inst3\|dout'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "1.700 ns" { lpf:inst3|lpm_add_sub:Add14|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~85 lpf:inst3|dout } "NODE_NAME" } } { "lpf.vhd" "" { Text "E:/quartus/program/2fsk_final/lpf.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.900 ns ( 66.78 % ) " "Info: Total cell delay = 18.900 ns ( 66.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.400 ns ( 33.22 % ) " "Info: Total interconnect delay = 9.400 ns ( 33.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Quartus II" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "28.300 ns" { lpf:inst3|p[2] lpf:inst3|Add1~77 lpf:inst3|Add2~350 lpf:inst3|lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] lpf:inst3|lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~55 lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~47 lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~41 lpf:inst3|lpm_add_sub:Add7|addcore:adder|unreg_res_node[4] lpf:inst3|lpm_add_sub:Add8|addcore:adder|unreg_res_node[4] lpf:inst3|lpm_add_sub:Add9|addcore:adder|unreg_res_node[4] lpf:inst3|lpm_add_sub:Add14|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] lpf:inst3|lpm_add_sub:Add14|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~85 lpf:inst3|dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "28.300 ns" { lpf:inst3|p[2] {} lpf:inst3|Add1~77 {} lpf:inst3|Add2~350 {} lpf:inst3|lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] {} lpf:inst3|lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] {} lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~55 {} lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~47 {} lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~41 {} lpf:inst3|lpm_add_sub:Add7|addcore:adder|unreg_res_node[4] {} lpf:inst3|lpm_add_sub:Add8|addcore:adder|unreg_res_node[4] {} lpf:inst3|lpm_add_sub:Add9|addcore:adder|unreg_res_node[4] {} lpf:inst3|lpm_add_sub:Add14|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] {} lpf:inst3|lpm_add_sub:Add14|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~85 {} lpf:inst3|dout {} } { 0.000ns 0.300ns 0.300ns 1.000ns 1.000ns 1.000ns 1.000ns 0.300ns 0.300ns 1.000ns 1.000ns 1.000ns 0.300ns 0.900ns } { 0.000ns 1.600ns 1.400ns 1.600ns 1.600ns 1.600ns 1.400ns 1.400ns 1.400ns 1.400ns 1.400ns 1.600ns 1.700ns 0.800ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.700 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 9.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 6; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "2fsk_final.bdf" "" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { -40 -288 -120 -24 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns div64:inst11\|divout 2 REG LC1_C24 17 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_C24; Fanout = 17; REG Node = 'div64:inst11\|divout'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { clk div64:inst11|divout } "NODE_NAME" } } { "div64.vhd" "" { Text "E:/quartus/program/2fsk_final/div64.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.500 ns) 6.300 ns div64:inst17\|divout 3 REG LC1_E3 41 " "Info: 3: + IC(2.900 ns) + CELL(0.500 ns) = 6.300 ns; Loc. = LC1_E3; Fanout = 41; REG Node = 'div64:inst17\|divout'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { div64:inst11|divout div64:inst17|divout } "NODE_NAME" } } { "div64.vhd" "" { Text "E:/quartus/program/2fsk_final/div64.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(0.000 ns) 9.700 ns lpf:inst3\|dout 4 REG LC1_A36 3 " "Info: 4: + IC(3.400 ns) + CELL(0.000 ns) = 9.700 ns; Loc. = LC1_A36; Fanout = 3; REG Node = 'lpf:inst3\|dout'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { div64:inst17|divout lpf:inst3|dout } "NODE_NAME" } } { "lpf.vhd" "" { Text "E:/quartus/program/2fsk_final/lpf.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 30.93 % ) " "Info: Total cell delay = 3.000 ns ( 30.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.700 ns ( 69.07 % ) " "Info: Total interconnect delay = 6.700 ns ( 69.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Quartus II" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "9.700 ns" { clk div64:inst11|divout div64:inst17|divout lpf:inst3|dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "9.700 ns" { clk {} clk~out {} div64:inst11|divout {} div64:inst17|divout {} lpf:inst3|dout {} } { 0.000ns 0.000ns 0.400ns 2.900ns 3.400ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 9.700 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 9.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns clk 1 CLK PIN_55 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 6; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "2fsk_final.bdf" "" { Schematic "E:/quartus/program/2fsk_final/2fsk_final.bdf" { { -40 -288 -120 -24 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.400 ns) + CELL(0.500 ns) 2.900 ns div64:inst11\|divout 2 REG LC1_C24 17 " "Info: 2: + IC(0.400 ns) + CELL(0.500 ns) = 2.900 ns; Loc. = LC1_C24; Fanout = 17; REG Node = 'div64:inst11\|divout'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { clk div64:inst11|divout } "NODE_NAME" } } { "div64.vhd" "" { Text "E:/quartus/program/2fsk_final/div64.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(0.500 ns) 6.300 ns div64:inst17\|divout 3 REG LC1_E3 41 " "Info: 3: + IC(2.900 ns) + CELL(0.500 ns) = 6.300 ns; Loc. = LC1_E3; Fanout = 41; REG Node = 'div64:inst17\|divout'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { div64:inst11|divout div64:inst17|divout } "NODE_NAME" } } { "div64.vhd" "" { Text "E:/quartus/program/2fsk_final/div64.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(0.000 ns) 9.700 ns lpf:inst3\|p\[2\] 4 REG LC5_A29 3 " "Info: 4: + IC(3.400 ns) + CELL(0.000 ns) = 9.700 ns; Loc. = LC5_A29; Fanout = 3; REG Node = 'lpf:inst3\|p\[2\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { div64:inst17|divout lpf:inst3|p[2] } "NODE_NAME" } } { "lpf.vhd" "" { Text "E:/quartus/program/2fsk_final/lpf.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns ( 30.93 % ) " "Info: Total cell delay = 3.000 ns ( 30.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.700 ns ( 69.07 % ) " "Info: Total interconnect delay = 6.700 ns ( 69.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "Quartus II" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "9.700 ns" { clk div64:inst11|divout div64:inst17|divout lpf:inst3|p[2] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "9.700 ns" { clk {} clk~out {} div64:inst11|divout {} div64:inst17|divout {} lpf:inst3|p[2] {} } { 0.000ns 0.000ns 0.400ns 2.900ns 3.400ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "Quartus II" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "9.700 ns" { clk div64:inst11|divout div64:inst17|divout lpf:inst3|dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "9.700 ns" { clk {} clk~out {} div64:inst11|divout {} div64:inst17|divout {} lpf:inst3|dout {} } { 0.000ns 0.000ns 0.400ns 2.900ns 3.400ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "9.700 ns" { clk div64:inst11|divout div64:inst17|divout lpf:inst3|p[2] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "9.700 ns" { clk {} clk~out {} div64:inst11|divout {} div64:inst17|divout {} lpf:inst3|p[2] {} } { 0.000ns 0.000ns 0.400ns 2.900ns 3.400ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.500 ns + " "Info: + Micro clock to output delay of source is 0.500 ns" {  } { { "lpf.vhd" "" { Text "E:/quartus/program/2fsk_final/lpf.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "Quartus II" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" {  } { { "lpf.vhd" "" { Text "E:/quartus/program/2fsk_final/lpf.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "Quartus II" 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "28.300 ns" { lpf:inst3|p[2] lpf:inst3|Add1~77 lpf:inst3|Add2~350 lpf:inst3|lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] lpf:inst3|lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~55 lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~47 lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~41 lpf:inst3|lpm_add_sub:Add7|addcore:adder|unreg_res_node[4] lpf:inst3|lpm_add_sub:Add8|addcore:adder|unreg_res_node[4] lpf:inst3|lpm_add_sub:Add9|addcore:adder|unreg_res_node[4] lpf:inst3|lpm_add_sub:Add14|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] lpf:inst3|lpm_add_sub:Add14|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~85 lpf:inst3|dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "28.300 ns" { lpf:inst3|p[2] {} lpf:inst3|Add1~77 {} lpf:inst3|Add2~350 {} lpf:inst3|lpm_add_sub:Add3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] {} lpf:inst3|lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] {} lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~55 {} lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~47 {} lpf:inst3|lpm_add_sub:Add7|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~41 {} lpf:inst3|lpm_add_sub:Add7|addcore:adder|unreg_res_node[4] {} lpf:inst3|lpm_add_sub:Add8|addcore:adder|unreg_res_node[4] {} lpf:inst3|lpm_add_sub:Add9|addcore:adder|unreg_res_node[4] {} lpf:inst3|lpm_add_sub:Add14|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] {} lpf:inst3|lpm_add_sub:Add14|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~85 {} lpf:inst3|dout {} } { 0.000ns 0.300ns 0.300ns 1.000ns 1.000ns 1.000ns 1.000ns 0.300ns 0.300ns 1.000ns 1.000ns 1.000ns 0.300ns 0.900ns } { 0.000ns 1.600ns 1.400ns 1.600ns 1.600ns 1.600ns 1.400ns 1.400ns 1.400ns 1.400ns 1.400ns 1.600ns 1.700ns 0.800ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "9.700 ns" { clk div64:inst11|divout div64:inst17|divout lpf:inst3|dout } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "9.700 ns" { clk {} clk~out {} div64:inst11|divout {} div64:inst17|divout {} lpf:inst3|dout {} } { 0.000ns 0.000ns 0.400ns 2.900ns 3.400ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "9.700 ns" { clk div64:inst11|divout div64:inst17|divout lpf:inst3|p[2] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "9.700 ns" { clk {} clk~out {} div64:inst11|divout {} div64:inst17|divout {} lpf:inst3|p[2] {} } { 0.000ns 0.000ns 0.400ns 2.900ns 3.400ns } { 0.000ns 2.000ns 0.500ns 0.500ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "Quartus II" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 3 " "Warning: Circuit may not operate. Detected 3 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "Quartus II" 0}