2fsk_final.sdc

全数字fsk调制解调的实现 verilog源码

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# Generated by : Version 7.2 Build 151 09/26/2007 SJ Web Edition
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# Project      : 2fsk_final
# Revision     : 2fsk_final
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# Date         : Mon Oct 27 10:30:24 中国标准时间 2008
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# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
#          In SDC, create_generated_clock auto-generates clock latency
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# Create generated clocks based on PLLs
derive_pll_clocks -use_tan_name
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# ** Clock Latency
#    -------------

# ** Clock Uncertainty
#    -----------------

# ** Multicycles
#    -----------
# ** Cuts
#    ----

# ** Input/Output Delays
#    -------------------




# ** Tpd requirements
#    ----------------

# ** Setup/Hold Relationships
#    ------------------------

# ** Tsu/Th requirements
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# ** Tco/MinTco requirements
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