2fsk_final.qsf

全数字fsk调制解调的实现 verilog源码

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		2fsk_final_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY ACEX1K
set_global_assignment -name DEVICE "EP1K30TC144-3"
set_global_assignment -name TOP_LEVEL_ENTITY 2fsk_final
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:07:09  OCTOBER 24, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name VHDL_FILE div8.vhd
set_global_assignment -name VHDL_FILE dpll.vhd
set_global_assignment -name VHDL_FILE f1_zb.vhd
set_global_assignment -name VHDL_FILE f2_zb.vhd
set_global_assignment -name VHDL_FILE lpf.vhd
set_global_assignment -name VHDL_FILE m5.vhd
set_global_assignment -name VHDL_FILE mux.vhd
set_global_assignment -name VHDL_FILE mx_7821.vhd
set_global_assignment -name VHDL_FILE pj.vhd
set_global_assignment -name VHDL_FILE pulse.vhd
set_global_assignment -name VHDL_FILE wf.vhd
set_global_assignment -name VHDL_FILE zx.vhd
set_global_assignment -name BDF_FILE 2fsk_final.bdf
set_global_assignment -name VHDL_FILE div64.vhd
set_global_assignment -name VHDL_FILE div16.vhd
set_global_assignment -name VHDL_FILE div128.vhd
set_global_assignment -name VHDL_FILE div1024.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE 2fsk_final.vwf
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_location_assignment PIN_55 -to clk
set_location_assignment PIN_102 -to din[7]
set_location_assignment PIN_101 -to din[6]
set_location_assignment PIN_100 -to din[5]
set_location_assignment PIN_99 -to din[4]
set_location_assignment PIN_98 -to din[3]
set_location_assignment PIN_97 -to din[2]
set_location_assignment PIN_96 -to din[1]
set_location_assignment PIN_95 -to din[0]
set_location_assignment PIN_17 -to dout1
set_location_assignment PIN_59 -to fsk[7]
set_location_assignment PIN_60 -to fsk[6]
set_location_assignment PIN_62 -to fsk[5]
set_location_assignment PIN_63 -to fsk[4]
set_location_assignment PIN_64 -to fsk[3]
set_location_assignment PIN_65 -to fsk[2]
set_location_assignment PIN_67 -to fsk[1]
set_location_assignment PIN_68 -to fsk[0]
set_location_assignment PIN_11 -to lpf
set_location_assignment PIN_14 -to mout
set_location_assignment PIN_10 -to pulse
set_location_assignment PIN_110 -to rd
set_location_assignment PIN_9 -to wf
set_location_assignment PIN_8 -to zx
set_location_assignment PIN_13 -to bsyn