2fsk_final.fit.summary

全数字fsk调制解调的实现 verilog源码

Fitter Status : Successful - Wed Oct 29 09:10:57 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Web Edition
Revision Name : 2fsk_final
Top-level Entity Name : 2fsk_final
Family : ACEX1K
Device : EP1K30TC144-3
Timing Models : Final
Total logic elements : 194 / 1,728 ( 11 % )
Total pins : 26 / 102 ( 25 % )
Total memory bits : 256 / 24,576 ( 1 % )
Total PLLs : 0