2fsk_final.sim.rpt

全数字fsk调制解调的实现 verilog源码

; Group bus channels in simulation results                                                   ; Off        ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On         ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off        ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; On         ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto       ; Auto          ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+----------------------------------------------------------------------------------+
; |2fsk_final|f1_zb:inst2|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|content ;
+----------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+-----------------------------------------------------------------------------------+
; |2fsk_final|f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|content ;
+-----------------------------------------------------------------------------------+
Memory report data cannot be output to ASCII.
Please use Quartus II to view the memory report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;     100.00 % ;
; Total nodes checked                                 ; 215          ;
; Total output ports checked                          ; 265          ;
; Total output ports with complete 1/0-value coverage ; 265          ;
; Total output ports with no 1/0-value coverage       ; 0            ;
; Total output ports with no 1-value coverage         ; 0            ;
; Total output ports with no 0-value coverage         ; 0            ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                 ;
+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                        ; Output Port Name                                                                                      ; Output Port Type ;
+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------+------------------+
; |2fsk_final|mx_7821:inst6|rd                                                                     ; |2fsk_final|mx_7821:inst6|rd                                                                          ; data_out0        ;
; |2fsk_final|m5:inst4|mout                                                                        ; |2fsk_final|m5:inst4|mout                                                                             ; data_out0        ;
; |2fsk_final|dpll:inst1|bsyn                                                                      ; |2fsk_final|dpll:inst1|bsyn                                                                           ; data_out0        ;
; |2fsk_final|lpf:inst3|dout                                                                       ; |2fsk_final|lpf:inst3|dout                                                                            ; data_out0        ;
; |2fsk_final|pj:inst7|dout                                                                        ; |2fsk_final|pj:inst7|dout                                                                             ; data_out0        ;
; |2fsk_final|mx_7821:inst6|dout[7]                                                                ; |2fsk_final|mx_7821:inst6|dout[7]                                                                     ; data_out0        ;
; |2fsk_final|wf:inst9|bitout                                                                      ; |2fsk_final|wf:inst9|bitout                                                                           ; data_out0        ;
; |2fsk_final|pulse:inst8|rout                                                                     ; |2fsk_final|pulse:inst8|rout                                                                          ; data_out0        ;
; |2fsk_final|div64:inst17|divout                                                                  ; |2fsk_final|div64:inst17|divout                                                                       ; data_out0        ;
; |2fsk_final|f1_zb:inst2|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment[0][7]           ; |2fsk_final|f1_zb:inst2|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]                         ; dataout          ;
; |2fsk_final|f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment[0][7]          ; |2fsk_final|f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[7]                        ; dataout          ;
; |2fsk_final|mux:inst5|dout[7]~32                                                                 ; |2fsk_final|mux:inst5|dout[7]~32                                                                      ; data_out0        ;
; |2fsk_final|f1_zb:inst2|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment[0][6]           ; |2fsk_final|f1_zb:inst2|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]                         ; dataout          ;
; |2fsk_final|f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment[0][6]          ; |2fsk_final|f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[6]                        ; dataout          ;
; |2fsk_final|mux:inst5|dout[6]~33                                                                 ; |2fsk_final|mux:inst5|dout[6]~33                                                                      ; data_out0        ;
; |2fsk_final|f1_zb:inst2|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment[0][5]           ; |2fsk_final|f1_zb:inst2|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[5]                         ; dataout          ;
; |2fsk_final|f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment[0][5]          ; |2fsk_final|f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[5]                        ; dataout          ;
; |2fsk_final|mux:inst5|dout[5]~34                                                                 ; |2fsk_final|mux:inst5|dout[5]~34                                                                      ; data_out0        ;
; |2fsk_final|f1_zb:inst2|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment[0][4]           ; |2fsk_final|f1_zb:inst2|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]                         ; dataout          ;
; |2fsk_final|f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment[0][4]          ; |2fsk_final|f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[4]                        ; dataout          ;
; |2fsk_final|mux:inst5|dout[4]~35                                                                 ; |2fsk_final|mux:inst5|dout[4]~35                                                                      ; data_out0        ;
; |2fsk_final|f1_zb:inst2|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment[0][3]           ; |2fsk_final|f1_zb:inst2|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]                         ; dataout          ;
; |2fsk_final|f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment[0][3]          ; |2fsk_final|f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[3]                        ; dataout          ;
; |2fsk_final|mux:inst5|dout[3]~36                                                                 ; |2fsk_final|mux:inst5|dout[3]~36                                                                      ; data_out0        ;
; |2fsk_final|f1_zb:inst2|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment[0][2]           ; |2fsk_final|f1_zb:inst2|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]                         ; dataout          ;
; |2fsk_final|f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|segment[0][2]          ; |2fsk_final|f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component|altrom:srom|q[2]                        ; dataout          ;