2fsk_final.map.rpt

全数字fsk调制解调的实现 verilog源码

Analysis & Synthesis report for 2fsk_final
Wed Oct 29 09:10:27 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Registers Removed During Synthesis
  9. General Register Statistics
 10. Source assignments for mx_7821:inst6|lpm_counter:count_rtl_0
 11. Source assignments for dpll:inst1|lpm_counter:count_rtl_1
 12. Source assignments for div16:inst13|lpm_counter:COUNT0_rtl_2
 13. Source assignments for f2_zb:inst19|lpm_counter:count_rtl_3
 14. Source assignments for f1_zb:inst2|lpm_counter:count_rtl_4
 15. Source assignments for lpf:inst3|lpm_add_sub:Add3|addcore:adder
 16. Source assignments for lpf:inst3|lpm_add_sub:Add6|addcore:adder
 17. Source assignments for lpf:inst3|lpm_add_sub:Add7|addcore:adder
 18. Source assignments for lpf:inst3|lpm_add_sub:Add8|addcore:adder
 19. Source assignments for lpf:inst3|lpm_add_sub:Add9|addcore:adder
 20. Source assignments for lpf:inst3|lpm_add_sub:Add14|addcore:adder
 21. Source assignments for div64:inst17|lpm_add_sub:Add0|addcore:adder
 22. Source assignments for div64:inst11|lpm_add_sub:Add0|addcore:adder
 23. Source assignments for div128:inst14|lpm_add_sub:Add0|addcore:adder
 24. Source assignments for div1024:inst15|lpm_add_sub:Add0|addcore:adder
 25. Parameter Settings for User Entity Instance: f1_zb:inst2|rom16_1:u1|lpm_rom:lpm_rom_component
 26. Parameter Settings for User Entity Instance: f2_zb:inst19|rom16_1:u1|lpm_rom:lpm_rom_component
 27. Parameter Settings for Inferred Entity Instance: mx_7821:inst6|lpm_counter:count_rtl_0
 28. Parameter Settings for Inferred Entity Instance: dpll:inst1|lpm_counter:count_rtl_1
 29. Parameter Settings for Inferred Entity Instance: div16:inst13|lpm_counter:COUNT0_rtl_2
 30. Parameter Settings for Inferred Entity Instance: f2_zb:inst19|lpm_counter:count_rtl_3
 31. Parameter Settings for Inferred Entity Instance: f1_zb:inst2|lpm_counter:count_rtl_4
 32. Parameter Settings for Inferred Entity Instance: lpf:inst3|lpm_add_sub:Add3
 33. Parameter Settings for Inferred Entity Instance: lpf:inst3|lpm_add_sub:Add6
 34. Parameter Settings for Inferred Entity Instance: lpf:inst3|lpm_add_sub:Add7
 35. Parameter Settings for Inferred Entity Instance: lpf:inst3|lpm_add_sub:Add8
 36. Parameter Settings for Inferred Entity Instance: lpf:inst3|lpm_add_sub:Add9
 37. Parameter Settings for Inferred Entity Instance: lpf:inst3|lpm_add_sub:Add14
 38. Parameter Settings for Inferred Entity Instance: div64:inst17|lpm_add_sub:Add0
 39. Parameter Settings for Inferred Entity Instance: div64:inst11|lpm_add_sub:Add0
 40. Parameter Settings for Inferred Entity Instance: div128:inst14|lpm_add_sub:Add0
 41. Parameter Settings for Inferred Entity Instance: div1024:inst15|lpm_add_sub:Add0
 42. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------+
; Analysis & Synthesis Summary                                          ;
+-----------------------------+-----------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Oct 29 09:10:27 2008   ;
; Quartus II Version          ; 7.2 Build 151 09/26/2007 SJ Web Edition ;
; Revision Name               ; 2fsk_final                              ;
; Top-level Entity Name       ; 2fsk_final                              ;
; Family                      ; ACEX1K                                  ;
; Total logic elements        ; 194                                     ;
; Total pins                  ; 26                                      ;
; Total memory bits           ; 256                                     ;
; Total PLLs                  ; 0                                       ;
+-----------------------------+-----------------------------------------+


+------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                            ;
+----------------------------------------------------------+---------------+---------------+
; Option                                                   ; Setting       ; Default Value ;
+----------------------------------------------------------+---------------+---------------+
; Device                                                   ; EP1K30TC144-3 ;               ;
; Top-level entity name                                    ; 2fsk_final    ; 2fsk_final    ;
; Family name                                              ; ACEX1K        ; Stratix II    ;
; Use smart compilation                                    ; Off           ; Off           ;
; Create Debugging Nodes for IP Cores                      ; Off           ; Off           ;
; Preserve fewer node names                                ; On            ; On            ;
; Disable OpenCore Plus hardware evaluation                ; Off           ; Off           ;
; Verilog Version                                          ; Verilog_2001  ; Verilog_2001  ;
; VHDL Version                                             ; VHDL93        ; VHDL93        ;
; State Machine Processing                                 ; Auto          ; Auto          ;
; Safe State Machine                                       ; Off           ; Off           ;
; Extract Verilog State Machines                           ; On            ; On            ;
; Extract VHDL State Machines                              ; On            ; On            ;
; Ignore Verilog initial constructs                        ; Off           ; Off           ;
; Add Pass-Through Logic to Inferred RAMs                  ; On            ; On            ;
; Parallel Synthesis                                       ; Off           ; Off           ;
; NOT Gate Push-Back                                       ; On            ; On            ;
; Power-Up Don't Care                                      ; On            ; On            ;
; Remove Redundant Logic Cells                             ; Off           ; Off           ;
; Remove Duplicate Registers                               ; On            ; On            ;
; Ignore CARRY Buffers                                     ; Off           ; Off           ;
; Ignore CASCADE Buffers                                   ; Off           ; Off           ;
; Ignore GLOBAL Buffers                                    ; Off           ; Off           ;
; Ignore ROW GLOBAL Buffers                                ; Off           ; Off           ;
; Ignore LCELL Buffers                                     ; Off           ; Off           ;
; Ignore SOFT Buffers                                      ; On            ; On            ;
; Limit AHDL Integers to 32 Bits                           ; Off           ; Off           ;
; Auto Implement in ROM                                    ; Off           ; Off           ;
; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K     ; Area          ; Area          ;
; Carry Chain Length -- FLEX 10K                           ; 32            ; 32            ;
; Cascade Chain Length                                     ; 2             ; 2             ;
; Auto Carry Chains                                        ; On            ; On            ;
; Auto Open-Drain Pins                                     ; On            ; On            ;
; Auto ROM Replacement                                     ; On            ; On            ;
; Auto RAM Replacement                                     ; On            ; On            ;
; Auto Clock Enable Replacement                            ; On            ; On            ;
; Auto Resource Sharing                                    ; Off           ; Off           ;