2fsk_final.map.summary

全数字fsk调制解调的实现 verilog源码

Analysis & Synthesis Status : Successful - Wed Oct 29 09:10:27 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Web Edition
Revision Name : 2fsk_final
Top-level Entity Name : 2fsk_final
Family : ACEX1K
Total logic elements : 194
Total pins : 26
Total memory bits : 256
Total PLLs : 0