div1024.vhd

全数字fsk调制解调的实现 verilog源码

LIBRARY ieee;
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_arith.all; 
USE ieee.std_logic_unsigned.all; 
LIBRARY work;

ENTITY div1024 IS 
	port
	(
		clk :  IN  STD_LOGIC;
		divout :  OUT  STD_LOGIC
	);
END div1024;

ARCHITECTURE bdf_type OF div1024 IS 
begin
PROCESS(CLK) 
variable COUNT0:STD_LOGIC_VECTOR(0 TO 9);
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF COUNT0 >= "0000000000" AND COUNT0 <"1111111111" 
THEN COUNT0 :=COUNT0+1;
ELSE COUNT0 :="0000000000";
END IF;
divout<=COUNT0(0);
END IF;
END PROCESS;
end bdf_type;