pj.vhd

来自「全数字fsk调制解调的实现 verilog源码」· VHDL 代码 · 共 21 行

library ieee;
use ieee.std_logic_1164.all;

entity pj is
port (din     :in  std_logic;
      clk     :in  std_logic;
      dout    :out std_logic);      
end pj;

architecture behav of pj is

begin

process(clk)
begin
   if clk'event and clk='1' then
        dout<=din;
   end if;             
end process;

end architecture behav;