ad_test.hier_info

多功能卡的源代码

|CPCI_exp
RAM_CE1_ <= core1:inst23.RAM_CE1_
CLK => altpll0:inst.inclk0
CLK => _232_to_fifo:inst5.clock
LHOLD => dma:inst6.LHOLD
LWR => dma:inst6.LWR
ADS_ => dma:inst6.ADS_
BLAST_ => dma:inst6.BLAST_
_232_sdin => 75.IN0
LA[2] => dma:inst6.LA[2]
LA[3] => dma:inst6.LA[3]
LA[4] => dma:inst6.LA[4]
LA[5] => dma:inst6.LA[5]
LA[6] => dma:inst6.LA[6]
LA[7] => dma:inst6.LA[7]
LA[8] => dma:inst6.LA[8]
LA[9] => dma:inst6.LA[9]
LD[0] <= dma:inst6.LD[0]
LD[0] <= 74541:inst11.Y1
LD[0] <= 5
LD[0] <= 74541:inst15.Y1
LD[0] <= _232_to_fifo:inst5.fifo_out[0]
LD[0] <= ad7864_fifo:inst7.fifo_out[0]
LD[0] <= adt7301_fifo:inst26.fifo_out[0]
LD[1] <= dma:inst6.LD[1]
LD[1] <= 74541:inst11.Y2
LD[1] <= 74541:inst15.Y2
LD[1] <= _232_to_fifo:inst5.fifo_out[1]
LD[1] <= ad7864_fifo:inst7.fifo_out[1]
LD[1] <= adt7301_fifo:inst26.fifo_out[1]
LD[2] <= dma:inst6.LD[2]
LD[2] <= 74541:inst11.Y3
LD[2] <= 74541:inst15.Y3
LD[2] <= _232_to_fifo:inst5.fifo_out[2]
LD[2] <= ad7864_fifo:inst7.fifo_out[2]
LD[2] <= adt7301_fifo:inst26.fifo_out[2]
LD[3] <= dma:inst6.LD[3]
LD[3] <= 74541:inst11.Y4
LD[3] <= 74541:inst15.Y4
LD[3] <= _232_to_fifo:inst5.fifo_out[3]
LD[3] <= ad7864_fifo:inst7.fifo_out[3]
LD[3] <= adt7301_fifo:inst26.fifo_out[3]
LD[4] <= dma:inst6.LD[4]
LD[4] <= 74541:inst11.Y5
LD[4] <= 74541:inst15.Y5
LD[4] <= _232_to_fifo:inst5.fifo_out[4]
LD[4] <= ad7864_fifo:inst7.fifo_out[4]
LD[4] <= adt7301_fifo:inst26.fifo_out[4]
LD[5] <= dma:inst6.LD[5]
LD[5] <= 74541:inst11.Y6
LD[5] <= 74541:inst15.Y6
LD[5] <= _232_to_fifo:inst5.fifo_out[5]
LD[5] <= ad7864_fifo:inst7.fifo_out[5]
LD[5] <= adt7301_fifo:inst26.fifo_out[5]
LD[6] <= dma:inst6.LD[6]
LD[6] <= 74541:inst11.Y7
LD[6] <= 74541:inst15.Y7
LD[6] <= _232_to_fifo:inst5.fifo_out[6]
LD[6] <= ad7864_fifo:inst7.fifo_out[6]
LD[6] <= adt7301_fifo:inst26.fifo_out[6]
LD[7] <= dma:inst6.LD[7]
LD[7] <= 74541:inst11.Y8
LD[7] <= 74541:inst15.Y8
LD[7] <= _232_to_fifo:inst5.fifo_out[7]
LD[7] <= ad7864_fifo:inst7.fifo_out[7]
LD[7] <= adt7301_fifo:inst26.fifo_out[7]
LD[8] <= dma:inst6.LD[8]
LD[8] <= 74541:inst13.Y1
LD[8] <= 74541:inst18.Y1
LD[8] <= _232_to_fifo:inst5.fifo_out[8]
LD[8] <= ad7864_fifo:inst7.fifo_out[8]
LD[8] <= adt7301_fifo:inst26.fifo_out[8]
LD[9] <= dma:inst6.LD[9]
LD[9] <= 74541:inst13.Y2
LD[9] <= 74541:inst18.Y2
LD[9] <= _232_to_fifo:inst5.fifo_out[9]
LD[9] <= ad7864_fifo:inst7.fifo_out[9]
LD[9] <= adt7301_fifo:inst26.fifo_out[9]
LD[10] <= dma:inst6.LD[10]
LD[10] <= 74541:inst13.Y3
LD[10] <= 74541:inst18.Y3
LD[10] <= _232_to_fifo:inst5.fifo_out[10]
LD[10] <= ad7864_fifo:inst7.fifo_out[10]
LD[10] <= adt7301_fifo:inst26.fifo_out[10]
LD[11] <= dma:inst6.LD[11]
LD[11] <= 74541:inst13.Y4
LD[11] <= 74541:inst18.Y4
LD[11] <= _232_to_fifo:inst5.fifo_out[11]
LD[11] <= ad7864_fifo:inst7.fifo_out[11]
LD[11] <= adt7301_fifo:inst26.fifo_out[11]
LD[12] <= dma:inst6.LD[12]
LD[12] <= 74541:inst13.Y5
LD[12] <= 74541:inst18.Y5
LD[12] <= _232_to_fifo:inst5.fifo_out[12]
LD[12] <= ad7864_fifo:inst7.fifo_out[12]
LD[12] <= adt7301_fifo:inst26.fifo_out[12]
LD[13] <= dma:inst6.LD[13]
LD[13] <= 74541:inst13.Y6
LD[13] <= 74541:inst18.Y6
LD[13] <= _232_to_fifo:inst5.fifo_out[13]
LD[13] <= ad7864_fifo:inst7.fifo_out[13]
LD[13] <= adt7301_fifo:inst26.fifo_out[13]
LD[14] <= dma:inst6.LD[14]
LD[14] <= 74541:inst13.Y7
LD[14] <= 74541:inst18.Y7
LD[14] <= _232_to_fifo:inst5.fifo_out[14]
LD[14] <= ad7864_fifo:inst7.fifo_out[14]
LD[14] <= adt7301_fifo:inst26.fifo_out[14]
LD[15] <= dma:inst6.LD[15]
LD[15] <= 74541:inst13.Y8
LD[15] <= 74541:inst18.Y8
LD[15] <= _232_to_fifo:inst5.fifo_out[15]
LD[15] <= ad7864_fifo:inst7.fifo_out[15]
LD[15] <= adt7301_fifo:inst26.fifo_out[15]
LD[16] <= dma:inst6.LD[16]
LD[17] <= dma:inst6.LD[17]
LD[18] <= dma:inst6.LD[18]
LD[19] <= dma:inst6.LD[19]
LD[20] <= dma:inst6.LD[20]
LD[21] <= dma:inst6.LD[21]
LD[22] <= dma:inst6.LD[22]
LD[23] <= dma:inst6.LD[23]
LD[24] <= dma:inst6.LD[24]
LD[25] <= dma:inst6.LD[25]
LD[26] <= dma:inst6.LD[26]
LD[27] <= dma:inst6.LD[27]
LD[28] <= dma:inst6.LD[28]
LD[29] <= dma:inst6.LD[29]
LD[30] <= dma:inst6.LD[30]
LD[31] <= dma:inst6.LD[31]
_422_sclk_1 => _422_to_fifo1:inst8.sclk
_422_sclk_1 => TEST_PIN[0].DATAIN
_422_sdin_1 => _422_to_fifo1:inst8.sdin
_422_sclk_2 => _422_to_fifo2:inst20.sclk
_422_sclk_2 => TEST_PIN[1].DATAIN
_422_sdin_2 => _422_to_fifo2:inst20.sdin
_422_sclk_3 => _422_to_fifo3:inst21.sclk
_422_sclk_3 => TEST_PIN[2].DATAIN
_422_sdin_3 => _422_to_fifo3:inst21.sdin
_422_sclk_4 => _422_to_fifo4:inst22.sclk
_422_sclk_4 => TEST_PIN[3].DATAIN
_422_sdin_4 => _422_to_fifo4:inst22.sdin
RAM_D[0] <= _422_to_fifo4:inst22.fifo_out[0]
RAM_D[0] <= _422_to_fifo3:inst21.fifo_out[0]
RAM_D[0] <= _422_to_fifo2:inst20.fifo_out[0]
RAM_D[0] <= _422_to_fifo1:inst8.fifo_out[0]
RAM_D[1] <= _422_to_fifo4:inst22.fifo_out[1]
RAM_D[1] <= _422_to_fifo3:inst21.fifo_out[1]
RAM_D[1] <= _422_to_fifo2:inst20.fifo_out[1]
RAM_D[1] <= _422_to_fifo1:inst8.fifo_out[1]
RAM_D[2] <= _422_to_fifo4:inst22.fifo_out[2]
RAM_D[2] <= _422_to_fifo3:inst21.fifo_out[2]
RAM_D[2] <= _422_to_fifo2:inst20.fifo_out[2]
RAM_D[2] <= _422_to_fifo1:inst8.fifo_out[2]
RAM_D[3] <= _422_to_fifo4:inst22.fifo_out[3]
RAM_D[3] <= _422_to_fifo3:inst21.fifo_out[3]
RAM_D[3] <= _422_to_fifo2:inst20.fifo_out[3]
RAM_D[3] <= _422_to_fifo1:inst8.fifo_out[3]
RAM_D[4] <= _422_to_fifo4:inst22.fifo_out[4]
RAM_D[4] <= _422_to_fifo3:inst21.fifo_out[4]
RAM_D[4] <= _422_to_fifo2:inst20.fifo_out[4]
RAM_D[4] <= _422_to_fifo1:inst8.fifo_out[4]
RAM_D[5] <= _422_to_fifo4:inst22.fifo_out[5]
RAM_D[5] <= _422_to_fifo3:inst21.fifo_out[5]
RAM_D[5] <= _422_to_fifo2:inst20.fifo_out[5]
RAM_D[5] <= _422_to_fifo1:inst8.fifo_out[5]
RAM_D[6] <= _422_to_fifo4:inst22.fifo_out[6]
RAM_D[6] <= _422_to_fifo3:inst21.fifo_out[6]
RAM_D[6] <= _422_to_fifo2:inst20.fifo_out[6]
RAM_D[6] <= _422_to_fifo1:inst8.fifo_out[6]
RAM_D[7] <= _422_to_fifo4:inst22.fifo_out[7]
RAM_D[7] <= _422_to_fifo3:inst21.fifo_out[7]
RAM_D[7] <= _422_to_fifo2:inst20.fifo_out[7]
RAM_D[7] <= _422_to_fifo1:inst8.fifo_out[7]
RAM_D[8] <= _422_to_fifo4:inst22.fifo_out[8]
RAM_D[8] <= _422_to_fifo3:inst21.fifo_out[8]
RAM_D[8] <= _422_to_fifo2:inst20.fifo_out[8]
RAM_D[8] <= _422_to_fifo1:inst8.fifo_out[8]
RAM_D[9] <= _422_to_fifo4:inst22.fifo_out[9]
RAM_D[9] <= _422_to_fifo3:inst21.fifo_out[9]
RAM_D[9] <= _422_to_fifo2:inst20.fifo_out[9]
RAM_D[9] <= _422_to_fifo1:inst8.fifo_out[9]
RAM_D[10] <= _422_to_fifo4:inst22.fifo_out[10]
RAM_D[10] <= _422_to_fifo3:inst21.fifo_out[10]
RAM_D[10] <= _422_to_fifo2:inst20.fifo_out[10]
RAM_D[10] <= _422_to_fifo1:inst8.fifo_out[10]
RAM_D[11] <= _422_to_fifo4:inst22.fifo_out[11]
RAM_D[11] <= _422_to_fifo3:inst21.fifo_out[11]
RAM_D[11] <= _422_to_fifo2:inst20.fifo_out[11]
RAM_D[11] <= _422_to_fifo1:inst8.fifo_out[11]
RAM_D[12] <= _422_to_fifo4:inst22.fifo_out[12]
RAM_D[12] <= _422_to_fifo3:inst21.fifo_out[12]
RAM_D[12] <= _422_to_fifo2:inst20.fifo_out[12]
RAM_D[12] <= _422_to_fifo1:inst8.fifo_out[12]
RAM_D[13] <= _422_to_fifo4:inst22.fifo_out[13]
RAM_D[13] <= _422_to_fifo3:inst21.fifo_out[13]
RAM_D[13] <= _422_to_fifo2:inst20.fifo_out[13]
RAM_D[13] <= _422_to_fifo1:inst8.fifo_out[13]
RAM_D[14] <= _422_to_fifo4:inst22.fifo_out[14]
RAM_D[14] <= _422_to_fifo3:inst21.fifo_out[14]
RAM_D[14] <= _422_to_fifo2:inst20.fifo_out[14]
RAM_D[14] <= _422_to_fifo1:inst8.fifo_out[14]
RAM_D[15] <= _422_to_fifo4:inst22.fifo_out[15]
RAM_D[15] <= _422_to_fifo3:inst21.fifo_out[15]
RAM_D[15] <= _422_to_fifo2:inst20.fifo_out[15]
RAM_D[15] <= _422_to_fifo1:inst8.fifo_out[15]
RAM_CE2 <= core1:inst23.RAM_CE2
RAM_WE_ <= core1:inst23.RAM_WE_
RAM_BHE_ <= core1:inst23.RAM_BHE_
RAM_BLE_ <= core1:inst23.RAM_BLE_
RAM_OE_ <= core1:inst23.RAM_OE_
LHOLDA <= dma:inst6.LHOLDA
READY_ <= dma:inst6.READY_
ad7864_read <= ad7864_fifo:inst7.ad7864_read
ad7864_eoc => ad7864_fifo:inst7.ad7864_eoc
ad7864_busy => ad7864_fifo:inst7.ad7864_busy
ad7864_data[0] => ad7864_fifo:inst7.ad_data[0]
ad7864_data[1] => ad7864_fifo:inst7.ad_data[1]
ad7864_data[2] => ad7864_fifo:inst7.ad_data[2]
ad7864_data[3] => ad7864_fifo:inst7.ad_data[3]
ad7864_data[4] => ad7864_fifo:inst7.ad_data[4]
ad7864_data[5] => ad7864_fifo:inst7.ad_data[5]
ad7864_data[6] => ad7864_fifo:inst7.ad_data[6]
ad7864_data[7] => ad7864_fifo:inst7.ad_data[7]
ad7864_data[8] => ad7864_fifo:inst7.ad_data[8]
ad7864_data[9] => ad7864_fifo:inst7.ad_data[9]
ad7864_data[10] => ad7864_fifo:inst7.ad_data[10]
ad7864_data[11] => ad7864_fifo:inst7.ad_data[11]
ad7864_cs <= ad7864_fifo:inst7.ad7864_cs
ad7864_conv <= ad7864_fifo:inst7.ad7864_conv
ad7864_sel1 <= ad7864_fifo:inst7.ad7864_sel1
ad7864_sel2 <= ad7864_fifo:inst7.ad7864_sel2
ad7864_sel3 <= ad7864_fifo:inst7.ad7864_sel3
ad7864_sel4 <= ad7864_fifo:inst7.ad7864_sel4
_7301_sclk <= adt7301_fifo:inst26.SCLK
_7301_DOUT => adt7301_fifo:inst26.DOUT
_7301_channel_cs[0] <= adt7301_fifo:inst26.channel_cs[0]
_7301_channel_cs[1] <= adt7301_fifo:inst26.channel_cs[1]
_7301_channel_cs[2] <= adt7301_fifo:inst26.channel_cs[2]
_7301_channel_cs[3] <= adt7301_fifo:inst26.channel_cs[3]
_7301_channel_cs[4] <= adt7301_fifo:inst26.channel_cs[4]
_7301_channel_cs[5] <= adt7301_fifo:inst26.channel_cs[5]
_7301_channel_cs[6] <= adt7301_fifo:inst26.channel_cs[6]
_7301_channel_cs[7] <= adt7301_fifo:inst26.channel_cs[7]
IO[0] => 74541:inst15.A1
IO[1] => 74541:inst15.A2
IO[2] => 74541:inst15.A3
IO[3] => 74541:inst15.A4
IO[4] => 74541:inst15.A5
IO[5] => 74541:inst15.A6
IO[6] => 74541:inst15.A7
IO[7] => 74541:inst15.A8
IO[8] => 74541:inst18.A1
IO[9] => 74541:inst18.A2
IO[10] => 74541:inst18.A3
IO[11] => 74541:inst18.A4
RAM_A[0] <= core1:inst23.RAM_ADDR[0]
RAM_A[1] <= core1:inst23.RAM_ADDR[1]
RAM_A[2] <= core1:inst23.RAM_ADDR[2]
RAM_A[3] <= core1:inst23.RAM_ADDR[3]
RAM_A[4] <= core1:inst23.RAM_ADDR[4]
RAM_A[5] <= core1:inst23.RAM_ADDR[5]
RAM_A[6] <= core1:inst23.RAM_ADDR[6]
RAM_A[7] <= core1:inst23.RAM_ADDR[7]
RAM_A[8] <= core1:inst23.RAM_ADDR[8]
RAM_A[9] <= core1:inst23.RAM_ADDR[9]
RAM_A[10] <= core1:inst23.RAM_ADDR[10]
RAM_A[11] <= core1:inst23.RAM_ADDR[11]
RAM_A[12] <= core1:inst23.RAM_ADDR[12]
RAM_A[13] <= core1:inst23.RAM_ADDR[13]
RAM_A[14] <= core1:inst23.RAM_ADDR[14]
RAM_A[15] <= core1:inst23.RAM_ADDR[15]
RAM_A[16] <= core1:inst23.RAM_ADDR[16]
RAM_A[17] <= core1:inst23.RAM_ADDR[17]
RAM_A[18] <= core1:inst23.RAM_ADDR[18]
RAM_A[19] <= core1:inst23.RAM_ADDR[19]
TEST_PIN[0] <= _422_sclk_1.DB_MAX_OUTPUT_PORT_TYPE
TEST_PIN[1] <= _422_sclk_2.DB_MAX_OUTPUT_PORT_TYPE
TEST_PIN[2] <= _422_sclk_3.DB_MAX_OUTPUT_PORT_TYPE
TEST_PIN[3] <= _422_sclk_4.DB_MAX_OUTPUT_PORT_TYPE


|CPCI_exp|core1:inst23
RHF_ONE_ => Selector1.IN3
RHF_ONE_ => fifo_sel~9.OUTPUTSELECT
RHF_ONE_ => fifo_sel~8.OUTPUTSELECT
RHF_ONE_ => fifo_sel~7.OUTPUTSELECT
RHF_ONE_ => fifo_sel~6.OUTPUTSELECT
RHF_ONE_ => operate_state~8.OUTPUTSELECT
RHF_ONE_ => operate_state~7.OUTPUTSELECT
RHF_ONE_ => operate_state~6.OUTPUTSELECT
RHF_ONE_ => operate_state~5.OUTPUTSELECT
RHF_ONE_ => half_full_state~0.IN1
RFE_ONE_ => ~NO_FANOUT~
RD_FIFO_ONE <= RD_FIFO_ONE~reg0.DB_MAX_OUTPUT_PORT_TYPE
RHF_TWO_ => operate_state~5.DATAA
RHF_TWO_ => fifo_sel~5.OUTPUTSELECT
RHF_TWO_ => fifo_sel~4.OUTPUTSELECT
RHF_TWO_ => fifo_sel~3.OUTPUTSELECT
RHF_TWO_ => operate_state~4.OUTPUTSELECT
RHF_TWO_ => operate_state~3.OUTPUTSELECT
RHF_TWO_ => operate_state~2.OUTPUTSELECT
RHF_TWO_ => half_full_state~0.IN0
RFE_TWO_ => ~NO_FANOUT~
RD_FIFO_TWO <= RD_FIFO_TWO~reg0.DB_MAX_OUTPUT_PORT_TYPE
RHF_THREE_ => operate_state~2.DATAA
RHF_THREE_ => fifo_sel~2.OUTPUTSELECT
RHF_THREE_ => fifo_sel~1.OUTPUTSELECT
RHF_THREE_ => operate_state~1.OUTPUTSELECT
RHF_THREE_ => operate_state~0.OUTPUTSELECT
RHF_THREE_ => half_full_state~1.IN0
RFE_THREE_ => ~NO_FANOUT~
RD_FIFO_THREE <= RD_FIFO_THREE~reg0.DB_MAX_OUTPUT_PORT_TYPE
RHF_FORE_ => operate_state~0.DATAA
RHF_FORE_ => fifo_sel~0.OUTPUTSELECT
RHF_FORE_ => half_full_state~2.IN0
RHF_FORE_ => operate_state~1.DATAA
RFE_FORE_ => ~NO_FANOUT~
RD_FIFO_FORE <= RD_FIFO_FORE~reg0.DB_MAX_OUTPUT_PORT_TYPE
RHF_232_ => half_full_state.IN1
RFE_232_ => ~NO_FANOUT~
RD_FIFO_232 <= RD_FIFO_232~reg0.DB_MAX_OUTPUT_PORT_TYPE
CLK => timer[19].CLK
CLK => timer[18].CLK
CLK => timer[17].CLK
CLK => timer[16].CLK
CLK => timer[15].CLK
CLK => timer[14].CLK
CLK => timer[13].CLK
CLK => timer[12].CLK
CLK => timer[11].CLK
CLK => timer[10].CLK
CLK => timer[9].CLK
CLK => timer[8].CLK
CLK => timer[7].CLK
CLK => timer[6].CLK
CLK => timer[5].CLK
CLK => timer[4].CLK
CLK => timer[3].CLK
CLK => timer[2].CLK
CLK => timer[1].CLK
CLK => timer[0].CLK
CLK => timer_start_flag.CLK
CLK => error_counter[0].CLK
CLK => error_counter[1].CLK
CLK => error_counter[2].CLK
CLK => error_counter[3].CLK
CLK => error_counter[4].CLK
CLK => error_counter[5].CLK
CLK => error_counter[6].CLK
CLK => error_counter[7].CLK
CLK => error_counter_enable.CLK
CLK => read_bkfifo_counter[0].CLK
CLK => read_bkfifo_counter[1].CLK
CLK => read_bkfifo_counter[2].CLK
CLK => read_bkfifo_counter[3].CLK
CLK => read_bkfifo_counter[4].CLK
CLK => read_bkfifo_counter[5].CLK