_422_txd1.v

来自「多功能卡的源代码」· Verilog 代码 · 共 154 行

module _422_txd1(sclk_2x,
				reset,
				sdout,
				sclk_out,
				txd_counter
				);	
input sclk_2x,reset;
output sclk_out,sdout;
output [30:0]txd_counter;
wire start;

reg sdout;
reg sclk_out;

reg [7:0]data_txd;
reg [4:0]counter;
reg [30:0]txd_counter;
reg [20:0]data_change_counter;
assign start=(txd_counter<1048576)?1'b1:1'b0;
//assign start=1'b1;

always @(posedge sclk_2x or negedge reset)
begin
	if(!reset)
	begin
		sclk_out<=1'b0;
		data_txd=8'd0;
		counter<=5'b10000;
		txd_counter<=31'd0;
		data_change_counter<=21'd0;
	end
	else if(start)
	begin
		case (counter)
		
		5'b10000://0th bit
		begin
			sclk_out<=1'b0;
			sdout<=data_txd[0];
			counter[4]<=~counter[4];
		end
		5'b00000:
		begin
			sclk_out<=1'b1;
			counter[0]<=~counter[0];
		end
		5'b00001://1th bit
		begin
			sclk_out<=1'b0;
			sdout<=data_txd[1];
			counter[1]<=~counter[1];
		end
		5'b00011:
		begin
			sclk_out<=1'b1;
			counter[0]<=~counter[0];
		end
		5'b00010://2th bit
		begin
			sclk_out<=1'b0;
			sdout<=data_txd[2];
			counter[2]<=~counter[2];
		end
		5'b00110:
		begin
			sclk_out<=1'b1;
			counter[0]<=~counter[0];
		end
		5'b00111://3th bit
		begin
			sclk_out<=1'b0;
			sdout<=data_txd[3];
			counter[1]<=~counter[1];	
		end
		5'b00101:
		begin
			sclk_out<=1'b1;
			counter[0]<=~counter[0];
		end
		5'b0100://4th bit
		begin
			sclk_out<=1'b0;
			sdout<=data_txd[4];
			counter[3]<=~counter[3];
		end
		5'b01100:
		begin
			sclk_out<=1'b1;
			counter[0]<=~counter[0];
		end
		5'b01101://5th bit
		begin
			sclk_out<=1'b0;
			sdout<=data_txd[5];
			counter[1]<=~counter[1];
		end
		5'b01111:
		begin
			sclk_out<=1'b1;
			counter[0]<=~counter[0];
		end
		5'b1110://6th bit
		begin
			sclk_out<=1'b0;
			sdout<=data_txd[6];
			counter[2]<=~counter[2];
		end
		5'b01010:
		begin
			sclk_out<=1'b1;
			counter[0]<=~counter[0];
		end
		5'b01011://7th bit
		begin
			sclk_out<=1'b0;
			sdout<=data_txd[7];
			counter[1]<=~counter[1];
		end
		5'b01001:
		begin
			sclk_out<=1'b1;
			txd_counter<=txd_counter+31'd1;
			data_change_counter<=data_change_counter+21'd1;
			counter[0]<=~counter[0];
		end
		//////////////////////////////////////////
		5'b01000:
		begin
			counter[4]<=~counter[4];
			//data_txd<=data_txd+8'd1;
			
			//=================================
			if(data_change_counter[12])
			begin
				data_txd<=data_txd+8'd1;
				data_change_counter<=21'd0;
			end
			
		end
		5'b11000:
		begin
			sclk_out<=1'b0;
			counter[3]<=~counter[3];
		end		
		endcase
	end
	else
	begin
		data_txd=8'd0;
		counter<=5'b10000;
		sclk_out<=1'b0;
	end
end
endmodule