_422_txd_power.v

来自「多功能卡的源代码」· Verilog 代码 · 共 28 行

module _422_txd_power(clock,reset,sclk2x);
input clock,reset;
output sclk2x;
//reg sclk2x;
reg [3:0]counter;
assign sclk2x=counter[0];
//assign sclk2x=counter[1];
always @(posedge clock or negedge reset)
begin
/*
	if(!reset)	begin	
		counter<=4'b0;	
		sclk2x<=1'b0;	
	end
	else if(counter==1)	begin
		counter<=counter+4'd1;
		sclk2x<=1'b1;
	end	
	else if(counter==4)	begin
		counter<=4'd0;
		sclk2x<=1'b0;
	end
	else counter<=counter+4'd1;
*/
if(!reset)	counter<=4'b0;
else	counter<=counter+4'd1;
end 
endmodule