clk_txd.v

多功能卡的源代码

//Author:liutong
//系统时钟输入，16倍时钟输出
//clk_sel==0时输出19200波特率的16倍时钟，clk_16x==1时输出9600波特率的16倍时钟
module clk_txd(sys_clock,clk_sel,rst,clk_txd,clk16x);

input sys_clock,clk_sel,rst;
output clk_txd,clk16x;
reg [3:0]clk_txd_mid;
/*
assign clk16x=sys_clock;
assign clk_txd=clk_txd_mid[3];
*/
reg	[7:0]counter;
reg [1:0]clk16x_mid;

parameter f_data1=54;
parameter f_data2=108;

assign clk16x=(clk_sel==1)?clk16x_mid[1]:clk16x_mid[0];
assign clk_txd=clk_txd_mid[3];

always @(posedge sys_clock or negedge rst)
begin
	if(!rst)	
	begin	
		counter<=8'd1;
		clk16x_mid<=2'b0;
	end
	else 
	begin 
		if(counter<f_data2)
		begin
			counter<=counter+8'd1;
			if (counter==f_data1) clk16x_mid<=clk16x_mid+2'd1;
		end
		else 
		begin	
			counter	<= 8'd1;	
			clk16x_mid<=clk16x_mid+2'd1;	
		end
	end	
end

always @(posedge clk16x or negedge rst)
begin	
	if(!rst)	clk_txd_mid<=4'd0;
	else clk_txd_mid<=clk_txd_mid+4'd1;
end
endmodule