num_test1.v

来自「多功能卡的源代码」· Verilog 代码 · 共 12 行

module NUM_TEST1(reset_,sclk,num);

input reset_,sclk;
output [31:0]num;
reg [31:0]num;
always @(posedge sclk or negedge reset_)
begin
	if(!reset_)	num<= 32'd0;
		
	else num<=num+ 32'd1;
end
endmodule