iic_ad75.v

I2C温度传感器ADT75的控制源码 使用verilog 状态机实现 易入门

										begin
											//main_state<= 2'b10;
											i2c_state  <= 4'b1001;//-------------------------------------
											inner_state <= stt;
													
										end 
								end							
					endcase	
			end




//################################_______________________________________________________________#################################


//==================================================================================================================

4'b1001://read

		begin 
			ST<=1;	
			case(inner_state) 
				
						stt: begin 						
								if(phase1) 
									begin 
										link<=1; 
										SDA_buf<=0; 
										
									end 
								if(phase3&link) 
									begin 							
										inner_state<=w1; 
										SDA_buf<=1; //------------------------------1
										link<=1; 
						
									end 
							end 
						w1: 
							if(phase3) 
								begin 
									SDA_buf<=0; //------------------------------0
									link<=1; 
									inner_state<=w2; 
								end 
						w2: 
							if(phase3) 
								begin 
									SDA_buf<=0; //------------------------------0
									link<=1; 
									inner_state<=w3; 
								end 
						w3: 
							if(phase3) 
								begin 
									SDA_buf<=1; //------------------------------1
									link<=1; 
									inner_state<=w4; 
								end 
						w4: 
							if(phase3) 
								begin 
									SDA_buf<=0; //-----------------------------A2
									link<=1; 
									inner_state<=w5; 
								end 
						w5: 
							if(phase3) 
								begin 
									SDA_buf<=0; //------------------------------A1
									link<=1; 
									inner_state<=w6; 
								end 
						w6: 
							if(phase3) 
								begin 
									SDA_buf<=0; //------------------------------A0
									link<=1; 
									inner_state<=w7; 
								end 
						w7: 
							if(phase3) 
								begin 
									SDA_buf<=1; //------------------------------R/W
									link<=1; 
									inner_state<=w8; 
								end 

						w8: 
							if(phase3) 
								begin 
									link<=0; //SDA TURN 
									inner_state<=ack; 
								end 


						RDdata8: 
							if(phase3) 
								begin 
									link<=0; //SDA TURN 
									inner_state<=ack_1; 
								end 

						ack: 
							begin 
								if(phase0) 
									SDA_buf<=SDA; 
								if(phase1) 
									begin 
										if(SDA_buf==1) 
											begin
											main_state<=2'b00; 
											end
									end 
									
							if(phase3) 
											begin
												link<=0; 
												inner_state<=R1; 
											end 
							   end 			

						R1: 
								begin 
									if(phase0) 
										SDA_buf<=SDA; 
									if(phase1) 
										begin 
											readData_reg[7:1]<=readData_reg[6:0]; 
											readData_reg[0]<=SDA; //------------------------------------------------@ D7
										end 
									if(phase3) 
										inner_state<=R2; 
								end 						
						R2: 
								begin 
									if(phase0) 
										SDA_buf<=SDA; 
									if(phase1) 
										begin 
											readData_reg[7:1]<=readData_reg[6:0];  
											readData_reg[0]<=SDA;//------------------------------------------------@ D6
										end 
									if(phase3) 
										inner_state<=R3; 
								end 	
								
						R3: 
								begin 
									if(phase0) 
										SDA_buf<=SDA; 
									if(phase1) 
										begin 
											readData_reg[7:1]<=readData_reg[6:0];  
											readData_reg[0]<=SDA;//------------------------------------------------@ D5
										end 
									if(phase3) 
										inner_state<=R4; 
								end 								 
							
						R4: 
								begin 
									if(phase0) 
										SDA_buf<=SDA; 
									if(phase1) 
										begin 
											readData_reg[7:1]<=readData_reg[6:0]; 
											readData_reg[0]<=SDA;//------------------------------------------------@ D4
										end 
									if(phase3) 
										inner_state<=R5; 
								end 							
						R5: 
								begin 
									if(phase0) 
										SDA_buf<=SDA; 
									if(phase1) 
										begin 
											readData_reg[7:1]<=readData_reg[6:0]; 
											readData_reg[0]<=SDA;//------------------------------------------------@ D3 
										end 
									if(phase3) 
										inner_state<=R6; 
								end 						
							
						R6: 
								begin 
									if(phase0) 
										SDA_buf<=SDA; 
									if(phase1) 
										begin 
											readData_reg[7:1]<=readData_reg[6:0];  
											readData_reg[0]<=SDA; //------------------------------------------------@ D2
										end 
									if(phase3) 
										inner_state<=R7; 
								end 						
							
						R7: 
								begin 
									if(phase0) 
										SDA_buf<=SDA; 
									if(phase1) 
										begin 
											readData_reg[7:1]<=readData_reg[6:0]; 
											readData_reg[0]<=SDA; //------------------------------------------------@ D1
										end 
									if(phase3) 
										inner_state<=R8; 
								end 						
						R8: 
								begin 
									if(phase0) 
										SDA_buf<=SDA; 
									if(phase1) 
										begin 
											readData_reg[7:1]<=readData_reg[6:0];  
											readData_reg[0]<=SDA; //------------------------------------------------@ D0
										end 
									if(phase3) 
										inner_state<=ack_2; 
								end 
								
						ack_2: 
								begin 
									if(phase3) 
										begin 
											link<=1; 
											SDA_buf<=0; 
											inner_state<=ack_4; 
										end 
								end 
								
						ack_4: 
								begin
									if(phase1) 
										begin
										link<=1;
										SDA_buf<=1;
										end 
									if(phase3)
										begin
											//main_state<= 2'b10;//***************************
											i2c_state  <= 4'b1011;
											inner_state <= stt;	
										
										end 
								end
				endcase 
			end 
//################################_______________________________________________________________################################
//################################                                                               #################################
//################################                          D_delay   state1                     #################################
//################################                                                               #################################
//################################_______________________________________________________________#################################	


4'b1011://delay##########################################3

		begin
             
					if(phase3)
					begin
							if(d_cnt==15'd1000)
								begin
									SDA_buf<=1; 
									link<=0; 
									i2c_state <= 4'b1111;
									inner_state <= stt;
									d_cnt<=15'd0;
								end
							else
								begin
									d_cnt<=d_cnt+15'd1;
									i2c_state <= 4'b1011;
								end
					end
							
				end
//------------------------------------------------------------------------------------------------------------
4'b1111://G_B
			begin
				MT<=1;				
			case(inner_state) 
				
						stt: begin 						
								if(phase1) 
									begin 
										link<=1; 
										SDA_buf<=0; 
										
									end 
								if(phase3&link) 
									begin 							
										inner_state<=w1; 
										SDA_buf<=1; //------------------------------1
										link<=1; 
						
									end 
							end 
						w1: 
							if(phase3) 
								begin 
									SDA_buf<=1; //------------------------------0
									link<=1; 
									inner_state<=w2; 
								end 
						w2: 
							if(phase3) 
								begin 
									SDA_buf<=1; //------------------------------0
									link<=1; 
									inner_state<=w3; 
								end 
						w3: 
							if(phase3) 
								begin 
									SDA_buf<=1; //------------------------------1
									link<=1; 
									inner_state<=w4; 
								end 
						w4: 
							if(phase3) 
								begin 
									SDA_buf<=1; //-----------------------------A2
									link<=1; 
									inner_state<=w5; 
								end 
						w5: 
							if(phase3) 
								begin 
									SDA_buf<=1; //------------------------------A1
									link<=1; 
									inner_state<=w6; 
								end 
						w6: 
							if(phase3) 
								begin 
									SDA_buf<=1; //------------------------------A0
									link<=1; 
									inner_state<=w7; 
								end 
						w7: 
							if(phase3) 
								begin 
									SDA_buf<=1; //------------------------------R/W
									link<=1; 
									inner_state<=w8; 
								end 
						w8: 
							if(phase3) 
								begin 
									link<=0; //SDA TURN 
									inner_state<=ack; 
								end 
						ack: 
							begin 
								if(phase0) 
									SDA_buf<=SDA; 
								if(phase1) 
									begin 
										if(SDA_buf==1) 
											begin
											main_state<=2'b00; 
											end
									end 
								if(phase3) 
									begin 
										link<=1; 
										SDA_buf<=0;//------------------------------0 for the 4 register adder's NUM0 all 0 add[7]
										inner_state<=stt; 										
										i2c_state<=4'b0000;
					
										
																								
									end 
							end 
				endcase

	end
//--------------------------------------------------------------------------------------------
			
	endcase			
end	


	endcase			
end	
end		
endmodule