📄 test0809.rpt
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Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC21 ale
| +----------------------------- LC17 c_state0
| | +--------------------------- LC23 c_state1
| | | +------------------------- LC18 c_state2
| | | | +----------------------- LC19 c_state3
| | | | | +--------------------- LC24 c_state4
| | | | | | +------------------- LC20 oe
| | | | | | | +----------------- LC32 q0
| | | | | | | | +--------------- LC25 q1
| | | | | | | | | +------------- LC26 q2
| | | | | | | | | | +----------- LC27 q3
| | | | | | | | | | | +--------- LC28 q4
| | | | | | | | | | | | +------- LC29 q5
| | | | | | | | | | | | | +----- LC30 q6
| | | | | | | | | | | | | | +--- LC31 q7
| | | | | | | | | | | | | | | +- LC22 start
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC21 -> * * * * - * * - - - - - - - - * | - * | <-- ale
LC17 -> * * * * * * * - - - - - - - - * | - * | <-- c_state0
LC23 -> * * * * * * * * * * * * * * * * | - * | <-- c_state1
LC18 -> - - - * - - - - - - - - - - - - | - * | <-- c_state2
LC19 -> - - - - * - - - - - - - - - - - | - * | <-- c_state3
LC24 -> - - - - - * - - - - - - - - - - | - * | <-- c_state4
LC20 -> * * * - * * * - - - - - - - - * | - * | <-- oe
LC22 -> * * * * * - * - - - - - - - - * | - * | <-- start
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- clk
13 -> - - - - - - - * - - - - - - - - | - * | <-- d0
12 -> - - - - - - - - * - - - - - - - | - * | <-- d1
9 -> - - - - - - - - - * - - - - - - | - * | <-- d2
5 -> - - - - - - - - - - * - - - - - | - * | <-- d3
6 -> - - - - - - - - - - - * - - - - | - * | <-- d4
7 -> - - - - - - - - - - - - * - - - | - * | <-- d5
4 -> - - - - - - - - - - - - - * - - | - * | <-- d6
8 -> - - - - - - - - - - - - - - * - | - * | <-- d7
11 -> - * - * - - * - - - - - - - - - | - * | <-- eoc
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\vhdl\test\test0809.rpt
test0809
** EQUATIONS **
clk : INPUT;
d0 : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
d7 : INPUT;
eoc : INPUT;
-- Node name is 'adda'
-- Equation name is 'adda', location is LC010, type is output.
adda = LCELL( GND $ VCC);
-- Node name is 'ale' = 'current_state3'
-- Equation name is 'ale', location is LC021, type is output.
ale = DFFE( _EQ001 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !ale & !c_state0 & !c_state1 & !oe & !start;
-- Node name is 'c_state0' = 'current_state0'
-- Equation name is 'c_state0', location is LC017, type is output.
c_state0 = DFFE( _EQ002 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !ale & c_state0 & !c_state1 & !eoc & !oe & !start
# ale & !c_state0 & !c_state1 & !oe & start;
-- Node name is 'c_state1' = 'current_state1'
-- Equation name is 'c_state1', location is LC023, type is output.
c_state1 = DFFE( _EQ003 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !ale & !c_state0 & !c_state1 & oe & !start;
-- Node name is 'c_state2' = 'current_state2~1'
-- Equation name is 'c_state2', location is LC018, type is output.
c_state2 = DFFE( _EQ004 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !ale & c_state0 & !c_state1 & !c_state2 & eoc & !start
# !ale & !c_state0 & !c_state1 & c_state2 & !start;
-- Node name is 'c_state3' = 'current_state3~1'
-- Equation name is 'c_state3', location is LC019, type is output.
c_state3 = DFFE( _EQ005 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !c_state0 & !c_state1 & !c_state3 & !oe & !start;
-- Node name is 'c_state4' = 'current_state4~1'
-- Equation name is 'c_state4', location is LC024, type is output.
c_state4 = DFFE( _EQ006 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !ale & !c_state0 & !c_state1 & !c_state4 & !oe;
-- Node name is 'oe' = 'current_state2'
-- Equation name is 'oe', location is LC020, type is output.
oe = DFFE( _EQ007 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !ale & c_state0 & !c_state1 & eoc & !oe & !start
# !ale & !c_state0 & !c_state1 & oe & !start;
-- Node name is 'q0' = 'regl0'
-- Equation name is 'q0', location is LC032, type is output.
q0 = DFFE( d0 $ GND, c_state1, VCC, VCC, VCC);
-- Node name is 'q1' = 'regl1'
-- Equation name is 'q1', location is LC025, type is output.
q1 = DFFE( d1 $ GND, c_state1, VCC, VCC, VCC);
-- Node name is 'q2' = 'regl2'
-- Equation name is 'q2', location is LC026, type is output.
q2 = DFFE( d2 $ GND, c_state1, VCC, VCC, VCC);
-- Node name is 'q3' = 'regl3'
-- Equation name is 'q3', location is LC027, type is output.
q3 = DFFE( d3 $ GND, c_state1, VCC, VCC, VCC);
-- Node name is 'q4' = 'regl4'
-- Equation name is 'q4', location is LC028, type is output.
q4 = DFFE( d4 $ GND, c_state1, VCC, VCC, VCC);
-- Node name is 'q5' = 'regl5'
-- Equation name is 'q5', location is LC029, type is output.
q5 = DFFE( d5 $ GND, c_state1, VCC, VCC, VCC);
-- Node name is 'q6' = 'regl6'
-- Equation name is 'q6', location is LC030, type is output.
q6 = DFFE( d6 $ GND, c_state1, VCC, VCC, VCC);
-- Node name is 'q7' = 'regl7'
-- Equation name is 'q7', location is LC031, type is output.
q7 = DFFE( d7 $ GND, c_state1, VCC, VCC, VCC);
-- Node name is 'start' = 'current_state4'
-- Equation name is 'start', location is LC022, type is output.
start = DFFE( _EQ008 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !ale & !c_state0 & !c_state1 & !oe & !start;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\vhdl\test\test0809.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,391K
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