test0809.vhd

vhdl 基于ADC0809 A/D转换控制器的设计实验

library ieee;
use ieee.std_logic_1164.all;
entity test0809 is
   port  (d : in std_logic_vector(7 downto 0);
          clk,eoc : in std_logic;
          ale,start,oe,adda : out std_logic;
          c_state:out std_logic_vector(4 downto 0);
          q:out std_logic_vector(7 downto 0));
end test0809;
architecture behav of test0809 is
signal current_state,next_state:std_logic_vector(4 downto 0);
  constant st0:std_logic_vector(4 downto 0):="00000";
  constant st1:std_logic_vector(4 downto 0):="11000";
  constant st2:std_logic_vector(4 downto 0):="00001";
  constant st3:std_logic_vector(4 downto 0):="00100";
  constant st4:std_logic_vector(4 downto 0):="00110";
  signal regl :std_logic_vector(7 downto 0);
  signal lock :std_logic;
begin
  adda<='1';q<=regl;start<=current_state(4);ale<=current_state(3);
  oe<=current_state(2);lock<=current_state(1);c_state<=current_state;
  com:process(current_state,eoc)begin
  case current_state is
  when st0=>next_state<=st1;
  when st1=>next_state<=st2;
  when st2=>if(eoc='1')then next_state<=st3;
        else next_state<=st2;
  end if;
  when st3=>next_state<=st4;
  when st4=>next_state<=st0;
  when others=>next_state<=st0;
  end case;
end process com;
reg:process (clk)
   begin
     if (clk'event and clk='1')then current_state<=next_state;
        end if;
   end process reg;
 latch1:process(lock)
      begin
       if lock='1'and lock'event then regl<=d;
         end if;
       end process latch1;
end behav;