x95288xl.vhd

VHDL的寄存器读写参考

--		end process;
	 ---------------------------------------------------------------------------------
	   process(fc07,crd,reg_fc07)        --read fc07 register
	     begin
	 	   if ((fc07='1') and (crd='0')) then
	 	      dd7 <= reg_fc07;
		   else 
		      dd7 <= "ZZZZZZZZ";
	 	   end if;
	   end process;
	 ---------------------------------------------------------------------------------
	   process(fc08,crd,ds1_int,ds2_int,ds3_int,ds4_int)  --read fc08 register
	     begin
		   if ((fc08='1') and (crd='0')) then
		      dd8(0) <= ds1_int;
			  dd8(1) <= ds2_int;
			  dd8(2) <= ds3_int;
			  dd8(3) <= ds4_int;
		   else 
		      dd8(3 downto 0) <= "ZZZZ";
		   end if;
	   end process;
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   --interrupt manager
      hdlc_int0 <=hdlc_int;
	  int0      <=hdlc_int0;
	  int1      <=ds1_int and ds2_int and ds3_int and ds4_int;
	  ds1_int   <=ds1_int0;
	  ds2_int   <=ds2_int0;
	  ds3_int   <=ds3_int0;
	  ds4_int   <=ds4_int0;
	  p8k       <=m8k;                --reserved
	  int2      <=p8k;
	  intout1   <=intout;
	  int3      <=intout1;  
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   --reset
      reset   <=sreset and xreset;
	  nreset  <= not(reset); 
      cpu_res <= reset;           
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    --sab82525 bus r/w signal
      dgate1  <=ccs525;
	  dirgate <= not(rw);
      cw525   <=rw;
      cpcs525 <=ccs525;
   -----------------------------------------------------------------------------------
    --sab82525 clock
	sab525clk: process(cmt4m,m8k)
	            begin
				  if (cmt4m='0' and cmt4m'event) then
				     if (m8k='0') then
					    counter5 <=  "000000000";
					 elsif (counter5= X"1ff") then
					    counter5 <=  "000000000";
				     else
					    counter5 <= counter5 + '1';
					 end if;

					 if (counter5(0)='1') then
					    c2m525s <= '1';
					 else 
					    c2m525s <= '0';
					 end if;
	              end if;
			  end process;

			  cmt4m0 <= not cmt4m;

			  process(cmt4m0,c2m525s)
			    begin
				  if (cmt4m0='1' and cmt4m0'event) then
				     c2m525 <= c2m525s;
				  end if;
			  end process;

   sab525sync: process(cmt4m,counter5)
	             begin
				   if (cmt4m='1' and cmt4m'event) then
				      if (counter5 = X"1ff") then
					     c8k5251 <= '1';
					  else 
					     c8k5251 <= '0';
					  end if;
				   end if;
				end process;

               process(cmt4m0,c8k5251)        --cmt4m positive and negative edge troggle 8K 
			     begin
				   if (cmt4m0='1' and cmt4m0'event) then
				      c8k5252 <= c8k5251;
                    end if;
 
				   if (cmt4m0='1' and cmt4m0'event) then
				       c8k525 <= c8k5252;
				   end if;
			   end process;
			   ds_2m <= c2m525s;
			   ds_8k <= c8k5251;

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   --DS21Q59 bus r/w signal
      ds1_fcs <=ds1_cs;
	  ds2_fcs <=ds2_cs;
	  ds3_fcs <=ds3_cs;
	  ds4_fcs <=ds4_cs;
      ds_dir  <= not(rw);
	  ds_gate <=ds1_cs and ds2_cs and ds3_cs and ds4_cs;
	  ds_oe   <=mstrb or (not rw);
	  ds_we   <=mstrb or rw;
	  ds_re   <=mstrb or (not rw);	  
	  ds1_ts0 <= saddr(6);
      ds2_ts0 <= saddr(6);
	  ds3_ts0 <= saddr(6);
	  ds4_ts0 <= saddr(6);
	  ds1_ts1 <= saddr(7);
	  ds2_ts1 <= saddr(7);
	  ds3_ts1 <= saddr(7);
	  ds4_ts1 <= saddr(7);
   ------------------------------------------------------------------------------------
    --DS21Q59 CLK
	   --      process(cmt4m,m8k,reset)
	   --         begin
		--		  if (cmt4m='0' and cmt4m'event) then
		--		     if (reset='0') then
		--			    counter6 <=  "000000000";
		--			 elsif (m8k='0') then
		--			    counter6 <=  "000000000";
		--			 elsif (counter6= X"1ff") then
		--			    counter6 <=  "000000000";
		--		     else
		--			    counter6 <= counter6 + '1';
		--			 end if;

		--			 if (counter6(0)='1') then
		--			    ds_2m <= '1';
		--			 else 
		--			    ds_2m <= '0';
		--			 end if;
	    --          end if;
		--	  end process;

		--	   process(cmt4m,counter6)
	     --        begin
		--		   if (cmt4m='1' and cmt4m'event) then
		--		      if (counter6 = X"1ff") then
		--			     ds_8k <= '1';
		--			  else 
		--			     ds_8k <= '0';
		--			  end if;
		--		   end if;
		--		end process;
   --------------------------------------------------------------------------------
		 ds1_sysclk <= ds_2m;
   	     ds2_sysclk <= ds_2m;
		 ds3_sysclk <= ds_2m;
		 ds4_sysclk <= ds_2m;

		 ds1_tclk   <= ds_2m;
         ds2_tclk   <= ds_2m;
		 ds3_tclk   <= ds_2m;
		 ds4_tclk   <= ds_2m;

         ds1_rsync  <= ds_8k;
		 ds2_rsync  <= ds_8k;
		 ds3_rsync  <= ds_8k;
		 ds4_rsync  <= ds_8k;

		 ds1_tsync  <= ds_8k;
		 ds2_tsync  <= ds_8k;
		 ds3_tsync  <= ds_8k;
		 ds4_tsync  <= ds_8k;

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   --CMT4M clk generator module  
     process(m16m,m4m,nreset)
      begin
	    if nreset='1' then
		   q0 <='0';
		elsif m16m'event and m16m='1' then
		   q0 <=m4m;
        end if;
	  end process;
  ----------------------------------------------------------------  
       m16m0 <= not m16m;
	  process(m16m0,q0)
	    begin 
          if m16m0'event and m16m0='1' then
		     q1<=q0;
		   end if;
	   end process;

	   m16m00 <= not m16m0;

	  process(m16m00,q1)
	     begin
		   if m16m00'event and m16m00='1' then
		      q2<=q1;
		   end if;
	   end process;
   ---------------------------------------------------------------
       m16m000 <= not m16m00;
	  process(m16m000,q2)
	    begin
		  if m16m000'event and m16m000='1' then
		     cmt4m<= not(q2);
		   end if;
	   end process;
	   p16m     <= m16m;
	   fpga_16m <= p16m;
	   p8k      <= m8k;
	   fpga_8k  <= p8k;
	   fpga_4m  <= cmt4m;

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	   process(ds1_outb,ds2_outb,ds3_outb,ds4_outb,reg_fc07(3 downto 0))
	     begin
		   case reg_fc07(3 downto 0) is 
		      when "0000"  => rclk <= ds1_outb(1);
			  when "0001"  => rclk <= ds1_outb(2);
			  when "0010"  => rclk <= ds1_outb(3);
			  when "0011"  => rclk <= ds1_outb(4);
			  when "0100"  => rclk <= ds2_outb(1);
			  when "0101"  => rclk <= ds2_outb(2);
			  when "0110"  => rclk <= ds2_outb(3);
			  when "0111"  => rclk <= ds2_outb(4);
              when "1000"  => rclk <= ds3_outb(1);
              when "1001"  => rclk <= ds3_outb(2);
			  when "1010"  => rclk <= ds3_outb(3);
			  when "1011"  => rclk <= ds3_outb(4);
			  when "1100"  => rclk <= ds4_outb(1);
			  when "1101"  => rclk <= ds4_outb(2);
			  when "1110"  => rclk <= ds4_outb(3);
			  when "1111"  => rclk <= ds4_outb(4);
			  when others  => null;
		   end case;
		end process;
	 --------------------------------------------------------------------------------
	    process(rclk,nreset)                          --8K clk generator
		   begin
			  if (nreset='1') then 
			      counter1 <= X"00";
			  elsif (rclk='1' and rclk'event) then
  			      counter1 <= counter1+'1';
				  if (counter1= X"FF") then
				     counter1 <= X"00";
				  end if;
		      end if;
		 end process;
        l8ko <= '1' when counter1= X"FF" else '0';
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  --clock light 
  --     process(m16m,nreset)              --16M light
--	     begin
--		   if (nreset='1') then
--		       counter2 <= X"000000";
--		   elsif (m16m='0' and m16m'event) then 
--		       counter2 <= counter2+'1';
--			   if (counter2 > X"7FFFFF") then
--			      counter2 <= X"000000";
--			   end if;
--		   end if;
--	   end process;
--	   led16m <= counter2(23);
	-----------------------------------------------------------------------
     --  process(cmt4m,nreset)            --4M light
	 --    begin
	 --     if (nreset='1') then
	 --	      counter3 <= "0000000000000000000000";
     --      elsif (cmt4m='0' and cmt4m'event) then
	 --	      counter3 <= counter3+'1';
	 --		  if (counter3 = X"3FFFFF") then
     --		      counter3 <= "0000000000000000000000";
	 --		   end if;
	 --	   end if;
	 --  end process;
--	   led4m <= counter2(21);
	 -----------------------------------------------------------------------
	 --  process(m8k,nreset)             --8k light
	 --     begin
	 --	   if (nreset='1') then
	 --	      counter4  <= "0000000000000";
     --     elsif (m8k='0' and m8k'event) then
	 --	      counter4 <= counter4+'1';
	 --		  if (counter4 = X"1FFF") then
	 --		      counter4 <= "0000000000000";
	 --		   end if;
	 --	   end if;
	 --  end process;
--	   led8k   <= counter2(12);
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end architecture logic;