top_pnadd32.vhd

32位元浮点数加法器,用于以VHDL编写的32位元CPU

-- to test all functions in pack_fun.vhd 

library IEEE;
use IEEE.std_logic_1164.all;
use work.pack_CC_fun.all;

entity GF_mult_4 is
  port(
      C:in STD_LOGIC_VECTOR(31 downto 0):="10111101101110000101000111101100";
      B:in STD_LOGIC_VECTOR(31 downto 0):="00111111101000000000000000000000";
      A:out STD_LOGIC_VECTOR(31 downto 0);     
      reset:in STD_LOGIC:='0'
      );

end GF_mult_4; 

architecture a of GF_mult_4 is
begin  
   A <= "00000000000000000000000000000000" when reset = '0' else
        fadd(C,B);
end a;