ps2.tan.summary

来自「使用verilog」· SUMMARY 代码 · 共 77 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -1.304 ns
From           : reset
To             : data_scanC:inst|tmp[1]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 36.577 ns
From           : convert:inst1|tmpASCII[6]
To             : seg7[3]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 14.058 ns
From           : reset
To             : seg7[3]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 8.743 ns
From           : reset
To             : convert:inst1|mydff:dff_component1|lpm_ff:lpm_ff_component|dffs[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 50.21 MHz ( period = 19.916 ns )
From           : convert:inst1|mydff:dff_component2|lpm_ff:lpm_ff_component|dffs[0]
To             : convert:inst1|tmpASCII[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : data_scanC:inst|started
To             : convert:inst1|tmpASCII[1]
From Clock     : clk
To Clock       : clk
Failed Paths   : 70

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 70

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