my_and.srr

此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA

#Build: Synplify 9.6A, Build 069R, Nov  3 2008
#install: D:\Actel\Libero_v8.5\Synplify\synplify_96A
#OS: Windows XP 5.1
#Hostname: GENGTIANXIANG

#Implementation: synthesis

#Sat Mar 07 10:59:21 2009

$ Start of Compile
#Sat Mar 07 10:59:21 2009

Synplicity Verilog Compiler, version 1.0, Build 157R, built Nov  5 2008
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved

@I::"D:\Actel\Libero_v8.5\Synplify\synplify_96A\lib\proasic\proasic3.v"
@I::"E:\work\EasyFPGA030\my_and\component\work\my_and\my_and.v"
Verilog syntax check successful!
Selecting top level module my_and
@N: CG364 :"D:\Actel\Libero_v8.5\Synplify\synplify_96A\lib\proasic\proasic3.v":1864:7:1864:9|Synthesizing module VCC

@N: CG364 :"D:\Actel\Libero_v8.5\Synplify\synplify_96A\lib\proasic\proasic3.v":1163:7:1163:9|Synthesizing module GND

@N: CG364 :"D:\Actel\Libero_v8.5\Synplify\synplify_96A\lib\proasic\proasic3.v":2:7:2:10|Synthesizing module AND2

@N: CG364 :"E:\work\EasyFPGA030\my_and\component\work\my_and\my_and.v":5:7:5:12|Synthesizing module my_and

@W: CL168 :"E:\work\EasyFPGA030\my_and\component\work\my_and\my_and.v":17:8:17:10|Pruning instance GND - not in use ...

@W: CL168 :"E:\work\EasyFPGA030\my_and\component\work\my_and\my_and.v":16:8:16:10|Pruning instance VCC - not in use ...

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Mar 07 10:59:21 2009

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Synplicity Proasic Technology Mapper, Version 9.4.2, Build 069R, Built Nov  7 2008 11:06:19
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved
Product Version Version 9.6A
@N: MF249 |Running in 32-bit mode.

Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB)

Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB)

Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB)

Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 87MB)

Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB)

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB)


Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication
Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB)

Writing Analyst data base E:\work\EasyFPGA030\my_and\synthesis\my_and.srm
@N: BN225 |Writing default property annotation file E:\work\EasyFPGA030\my_and\synthesis\my_and.map.
Finished Writing Netlist Databases (Time elapsed 0h:00m:01s; Memory used current: 86MB peak: 87MB)

Writing EDIF Netlist and constraint files
Version 9.6A
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 87MB)



##### START OF TIMING REPORT #####[
# Timing Report written on Sat Mar 07 10:59:25 2009
#


Top view:               my_and
Library name:           PA3
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.42, P = 1.30, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        proasic3
Paths requested:        5
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Report for cell my_and.verilog
  Core Cell usage:
              cell count     area count*area
              AND2     1      1.0        1.0
               GND     1      0.0        0.0
               VCC     1      0.0        0.0


                   -----          ----------
             TOTAL     3                 1.0


  IO Cell usage:
              cell count
             INBUF     2
            OUTBUF     1
                   -----
             TOTAL     3


Core Cells         : 1 of 768 (0%)
IO Cells           : 3 of 83 (4%)
Mapper successful!
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
# Sat Mar 07 10:59:25 2009

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