par2ser.txt

来自「these files are written in verilog but i」· 文本 代码 · 共 20 行

   `timescale 1ns/1ps
      module parallel_2_serial (serial_out, parallel_in, clock, clk_8,reset_n);   
        output serial_out;
        input clock,clk_8;
        input reset_n;
        input [7:0] parallel_in;
        reg [7:0] parallel_r;
        always @(posedge clock or posedge reset_n)
         begin
           if (reset_n)
            parallel_r <= 0;
            else if (clk_8)
            parallel_r <= parallel_in;
           else if (clock)
            parallel_r <= {1'b0, parallel_r[7:1]};
          end
          assign serial_out = parallel_r[0];
        endmodule