oneshot_rx.txt

these files are written in verilog but i am uploading in text format

`timescale 1ns/1ps
module oneshot_rx(osin_rx,clk1,osout_rx,load_rx);
input osin_rx;
input clk1;
output osout_rx,load_rx;
reg osout_rx,load_rx; 
reg count=1'b1;
always @(posedge osin_rx or posedge osout_rx)
begin
  if(osin_rx)
   begin
   if(count)
     begin
        if(osout_rx)
           load_rx<= 0;
        else
           load_rx <= 1;
      count<=1'b0; 
     end
  end
if(osout_rx)
	 load_rx<= 0;
end

always @(posedge clk1)
begin
osout_rx <= load_rx;
end
endmodule