main.txt

these files are written in verilog but i am uploading in text format

`timescale 1ns/1ps
module gs(clk,load,reset, msg_out);
    input clk,load,reset;
    output msg_out;
    wire busy,frame,overrun,readyo;
    wire [3:0]CSo;
    wire [7:0]dout_out;
    wire clk1,q61,q62,gs,osout,data,shift,clk_8,baud16,txd,ready,q61_rx,q62_rx,serial_out,gs_rx,load_rx,osout_rx;
    wire [7:0]dOut;
    wire [3:0] CS;
    clock in1(clk,clk1);
    lfsrn11 in2(q61, clk1, osout);
    lfsrn12 in3(q62, clk1, osout);
     sum    in4( q61,q62,gs);
     mul in5(gs,osout,data);
     oneshot in6(load,clk1,osout);
     ser_par_conv  in7(dOut, clk1, data);
     uarttx in8(dOut,load,clk,clk_8,reset,shift,txd,ready,CS);
     baud1 in9(clk,shift);
      clk_8  in10(clk1,clk_8);
      uartrx in11(dout_out,clk,baud16,reset,txd,frame,overrun,readyo,busy,CSo);
      baud16 in12(clk,baud16);
      parallel_2_serial  in13(serial_out, dout_out, clk1, clk_8,reset);
      sum_rx in14(q61_rx,q62_rx,gs_rx);
      lfsrn11_rx in15(q61_rx, clk1, load_rx);
      lfsrn12_rx in16(q62_rx, clk1,load_rx);
      mul_rx in17(gs_rx,serial_out,msg_out);
      oneshot_rx  in18(serial_out,clk1,osout_rx,load_rx);
 endmodule
 
 module test_gs;
     reg clk,load,reset;
     wire msg_out;
     gs inq1(clk,load,reset,msg_out);
     initial
     begin
         clk=1'b0;
         reset=1'b0;
         #100 reset=1'b1;
         #100 reset=1'b0;
         load=1'b0;
         #30 load =1'b1;
          
     end
     always
     #20clk=~clk;
 endmodule