mul_rx.txt

these files are written in verilog but i am uploading in text format

`timescale 1ns/1ps
module mul_rx(gs_rx,serial_out,msg_out);
input gs_rx,serial_out;
output msg_out;
reg msg_out ;
//always@(posedge load)
//msg<=1'b1;
always@*
  msg_out<=gs_rx^serial_out;
endmodule