📄 ls138.tan.rpt
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Timing Analyzer report for LS138
Sat Nov 29 23:56:12 2008
Version 5.1 Build 176 10/26/2005 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 9.670 ns ; G2 ; Q0 ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F484C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+---------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A ; None ; 9.670 ns ; G2 ; Q0 ;
; N/A ; None ; 9.649 ns ; G2 ; Q6 ;
; N/A ; None ; 9.627 ns ; G2 ; Q7 ;
; N/A ; None ; 9.625 ns ; G2 ; Q5 ;
; N/A ; None ; 9.411 ns ; G2 ; Q1 ;
; N/A ; None ; 9.410 ns ; G2 ; Q4 ;
; N/A ; None ; 9.409 ns ; G2 ; Q3 ;
; N/A ; None ; 9.330 ns ; G1 ; Q0 ;
; N/A ; None ; 9.309 ns ; G1 ; Q6 ;
; N/A ; None ; 9.287 ns ; G1 ; Q7 ;
; N/A ; None ; 9.285 ns ; G1 ; Q5 ;
; N/A ; None ; 9.145 ns ; G2 ; Q2 ;
; N/A ; None ; 9.125 ns ; C ; Q0 ;
; N/A ; None ; 9.104 ns ; C ; Q6 ;
; N/A ; None ; 9.083 ns ; C ; Q7 ;
; N/A ; None ; 9.081 ns ; C ; Q5 ;
; N/A ; None ; 9.071 ns ; G1 ; Q1 ;
; N/A ; None ; 9.070 ns ; G1 ; Q4 ;
; N/A ; None ; 9.069 ns ; G1 ; Q3 ;
; N/A ; None ; 9.018 ns ; B ; Q6 ;
; N/A ; None ; 9.017 ns ; B ; Q0 ;
; N/A ; None ; 8.982 ns ; B ; Q5 ;
; N/A ; None ; 8.979 ns ; B ; Q7 ;
; N/A ; None ; 8.867 ns ; C ; Q1 ;
; N/A ; None ; 8.866 ns ; C ; Q4 ;
; N/A ; None ; 8.865 ns ; C ; Q3 ;
; N/A ; None ; 8.855 ns ; C ; Q2 ;
; N/A ; None ; 8.809 ns ; A ; Q6 ;
; N/A ; None ; 8.809 ns ; A ; Q0 ;
; N/A ; None ; 8.805 ns ; G1 ; Q2 ;
; N/A ; None ; 8.776 ns ; A ; Q5 ;
; N/A ; None ; 8.771 ns ; A ; Q7 ;
; N/A ; None ; 8.766 ns ; B ; Q4 ;
; N/A ; None ; 8.759 ns ; B ; Q2 ;
; N/A ; None ; 8.755 ns ; B ; Q1 ;
; N/A ; None ; 8.749 ns ; B ; Q3 ;
; N/A ; None ; 8.558 ns ; A ; Q4 ;
; N/A ; None ; 8.551 ns ; A ; Q2 ;
; N/A ; None ; 8.547 ns ; A ; Q1 ;
; N/A ; None ; 8.546 ns ; A ; Q3 ;
+-------+-------------------+-----------------+------+----+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
Info: Processing started: Sat Nov 29 23:56:12 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LS138 -c LS138 --timing_analysis_only
Info: Longest tpd from source pin "G2" to destination pin "Q0" is 9.670 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_M8; Fanout = 1; PIN Node = 'G2'
Info: 2: + IC(3.964 ns) + CELL(0.366 ns) = 5.417 ns; Loc. = LC_X36_Y1_N6; Fanout = 8; COMB Node = 'process0~0'
Info: 3: + IC(0.395 ns) + CELL(0.075 ns) = 5.887 ns; Loc. = LC_X36_Y1_N3; Fanout = 1; COMB Node = 'ALLQ~83'
Info: 4: + IC(1.379 ns) + CELL(2.404 ns) = 9.670 ns; Loc. = PIN_M7; Fanout = 0; PIN Node = 'Q0'
Info: Total cell delay = 3.932 ns ( 40.66 % )
Info: Total interconnect delay = 5.738 ns ( 59.34 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Nov 29 23:56:12 2008
Info: Elapsed time: 00:00:01
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