test_cpu.v

来自「精通verilog HDL语言编程的一个不错的cpu 代码」· Verilog 代码 · 共 60 行

	`timescale 1ns/10ps
	module test_cpu;
	
	reg	nrst,clk;
	wire	load,iowen;
	wire[7:0] ioaddr,iodata;
	wire	ATPG;
	
	always #5 clk=~clk;
	initial
	 begin
	     clk=0;
	     nrst=0;
	     #100  nrst=1;
	     
	 end    
	
	CPU CPU(//input
		.nrst	(nrst),
		.clk	(clk),
		//IO interface
		.load	(load),		
		.iowen	(iowen),
		.ioaddr	(ioaddr),
		.iodata	(iodata),

		//test mode
		.ATPG	(ATPG));

	IO IO(//input	
		.nrst	(nrst),
		.clk	(clk),
		//output
		.load	(load),		
		.iowen	(iowen),
		.addr	(ioaddr),
		.dout	(iodata) );

	initial
	begin
//	 `ifdef test1
//	    $dumpfile("./vcd/test.1.vcd");
//	 `endif
	 `ifdef test2
	    $dumpfile("./vcd/test.2.vcd");
	 `endif


//	$fsdbDumpvars(0,top);
	end
	endmodule