cpu.v

精通verilog HDL语言编程的一个不错的cpu 代码

	`timescale 1ns/10ps
	module CPU(//input
		nrst,clk,
		//IO interface
		load,
		iowen,ioaddr,iodata,
		ATPG
		//output
		);

	input	nrst,clk;
	input	load,iowen;
	input[7:0] ioaddr,iodata;
	input	ATPG;

	wire	ctl_wen,reg_add,reg_sub,reg_and,reg_or,reg_shl;
	wire	reg_shr,direct,reg_unchg,reg_anm,reg_orm;
	wire[7:0] ctl_addr,ctl_din,mem_dout;
	wire[7:0] mem_addr=load?ioaddr:ctl_addr;
	wire[7:0] mem_din=load?iodata:ctl_din;
	wire	mem_wen=load? iowen:ctl_wen;

	wire[7:0] ctrladdr,ctrldin;
	wire[7:0] mem_addr1=load?ioaddr:ctrladdr;
	wire[7:0] mem_din1=load?iodata:8'hff;
	wire	mem_wen1=load? iowen:1'b1;

	wire[1:0] rega_sel,regb_sel,regc_sel;
	wire[7:0] data2reg,rega2ctl,regb2ctl;
	wire[1:0] curnt_state;
	wire clki;

	assign clki=clk;

	memory I_mem1(
		//input
		.CLK	(clki),
		.CEN	(1'b0),
		.WEN	(mem_wen),
		.A	(mem_addr),
		.D	(mem_din),
		//output
		.Q	(mem_dout));

	control control(
		//input
		.nrst	(nrst),
		.clk	(clki),
		.exe_program	(~load),
		.mem_dout	(mem_dout),
		.rega2ctl	(rega2ctl),
		.regb2ctl	(regb2ctl),

		.ctl_wen	(ctl_wen),
		.ctl_din	(ctl_din),
		.ctl_addr	(ctl_addr),
		.rega_sel	(rega_sel),
		.regb_sel	(regb_sel),

		.regc_sel	(regc_sel),
		.data2reg	(data2reg),

		.curnt_state	(curnt_state),
		.reg_add	(reg_add),
		.reg_sub	(reg_sub),
		.reg_and	(reg_and),
		.reg_or	(reg_or),
		.reg_shl	(reg_shl),

		.reg_shr	(reg_shr),
		.direct	(direct),
		.reg_unchg	(reg_unchg),
		.reg_anm	(reg_anm),
		.reg_orm	(reg_orm));


	alu alu(
		//input
		.nrst	(nrst),
		.clk	(clki),

		//control signals
		.rega_sel	(rega_sel),
		.regb_sel	(regb_sel),
		.regc_sel	(regc_sel),
		.data2reg	(data2reg),
		.curnt_state	(curnt_state),
		.reg_add	(reg_add),
		.reg_sub	(reg_sub),
		.reg_and	(reg_and),
		.reg_or		(reg_or),
		.reg_shl	(reg_shl),
		.reg_shr	(reg_shr),

		.reg_unchg	(reg_unchg),
		.direct		(direct),
		.reg_anm	(reg_anm),
		.reg_orm	(reg_orm),

		//output
		.rega2ctl	(rega2ctl),
		.regb2ctl	(regb2ctl)
		);
	endmodule