gwok_1_d

来自「精通verilog HDL语言编程的一个不错的cpu 代码」· 代码 · 共 15 行

! \VCS_INCR_017\ \6.0.1\ \test_cpu\ 1 0 
! 1 0 3 170d 353aa877 0 ed0c4d4e 0 
! 30000171 0 4 7 5 0 0 1 3bbc263b 0 100 100 2 0 1 1 0 
! (unknown) 499b7c0c 
! 390000 0 0 0 0 0 0 2 d 0 0 0 0 0 0 0 
! \CPU\ 1 \IO\ 1 
! 1 0 2 2 0  1 0 2 2 1  1 0 2 2 2  1 0 2 2 3  8000008 0 2 2 4  8000008 0 2 2 5  1 0 2 2 6  1 0 2 2 0  
! 1 0 2 2 1  1 0 4 4 2  1 0 4 4 3  8000008 0 4 4 4  8000008 0 4 4 5  
! d 
! 3 a1000000 0 7c 0 0 0 0 0 0 0 0 0 0 0 0 
! 0 
! 0 
! END OF INCREMENTAL COMPILATION DATA, RADIFY VCD DATA STARTS 
! 0 0 0