makefile

精通verilog HDL语言编程的一个不错的cpu 代码

# Makefile generated by VCS to build your model
# This file may be modified; VCS will not overwrite it unless -Mupdate is used

# define default verilog source directory 
VSRC=..

# Note: if make gives you errors about include, either get gmake, or
# replace the following line with the contents of the file filelist,
# EACH TIME IT CHANGES
# included file defines OBJS, and is automatically generated by vcs
include filelist

# Choose name of executable 
PRODUCT=$(VSRC)/simv

# Path to runtime library
CMODLIB=
RUNTIME=/synopsys/vcs6.0.1/sun_sparc_solaris_5.5.1/lib/libvcs$(VCS_LIBEXT).a

# Select your favorite compiler

# SOLARIS 2 : Use either VCS_CC=gcc or VCS=cc (if you have it)
#VCS_CC=gcc -w  # GNU cc
#VCS_CC=apcc -w # Apogee cc
VCS_CC=cc -w   # Sun Pro cc
# Loader
LD=/usr/ccs/bin/ld
# Loader Flags
LDFLAGS=

# C run time startup
CRT0=
# Machine specific libraries
SYSLIBS=-lm -lc  -ldl

# Default defines
SHELL=/bin/sh

VCSTMPSPECARG=
VCSTMPSPECENV=
# NOTE: if you have little space in /tmp, but plenty in /foo,
# and 1) you are using Sun's cc, uncomment the next line
#VCSTMPSPECARG=-temp=/foo
# or  2) you are using gcc, uncomment the next line
#VCSTMPSPECENV=TMPDIR=/foo

TMPSPECARG=$(VCSTMPSPECARG)
TMPSPECENV=$(VCSTMPSPECENV)
CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG)

# C flags for compilation
CFLAGS=-O -D__svr4__    

LIBS=-lnsl -lsocket -ldl 
DOTLIBS=

product : $(PRODUCT)
	@echo $(PRODUCT) up to date
objects : $(OBJS)

clean   :
	rm -f $(VCS_OBJS)

clobber : clean
	rm -f $(PRODUCT)

$(PRODUCT) : $(OBJS) $(DOTLIBS) $(CMODLIB) $(RUNTIME)
	-if [ -x $(PRODUCT) ]; then chmod -x $(PRODUCT); fi
	$(LD) $(CRT0) -o $(PRODUCT) $(LDFLAGS) $(OBJS) $(LIBS)     $(CMODLIB) $(RUNTIME) $(SYSLIBS)