io.v

精通verilog HDL语言编程的一个不错的cpu 代码

	`timescale 1ns/10ps
	module IO(//input
		nrst,clk,

		//output
		load,iowen,addr,dout
	);
	input	nrst,clk;
	output	load;
	output	iowen;
	output[7:0] addr,dout;

	parameter vector_path="./vector";
	parameter ADD=4'b0000,
                  SUB=4'b0001,
                  ADI=4'b0010,
                  SBI=4'b0011,
                  ANM=4'b0100,
                  ORM=4'b0101,
                  ANP=4'b0110,
                  ORR=4'b0111,
                  SHL=4'b1000,
                  SHR=4'b1001,
                  LBM=4'b1010,
                  SBM=4'b1011,
                  MOV=4'b1100,
                  JEQ=4'b1101,
                  JLS=4'b1110,
                  JMP=4'b1111;

	reg[127:0] str,str1,str2,str3,str4;
	reg[47:0]  command;
	reg[15:0]  data_byte;
	reg[7:0]   data,addr=0;
	reg[15:0]  reg1,reg2;
	reg[1:0]   rg1,rg2,rg1_o,rg2_o,rg3_o;
	reg[7:0]   dout;
	reg	   load=1;
	reg        iowen=1;
	integer    fid,i;

	reg[127:0]  r;

	initial
	 begin
	 // `ifdef test1
		fid=$fopenr({vector_path,"/","test1.txt"});
	//  `endif

	  `ifdef test2
		fid=$fopen({vector_path,"/","test2.txt"},"r");
	  `endif
	 end

	initial
	begin
	  @(posedge clk);
	  @(posedge nrst);
	  @(posedge clk);
	forever
	begin:read_program_in
	  r=$fgets(str,128,fid);     //!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
	    //$display("1: str: %h",str);
	    getcmd(str,str1);
	    //$display("2: str: %h",str1);

	if(command=="end") 
	begin
	 load=0;
	 $display("End of the assembly code");
	 $fclose(fid);
	  @(posedge clk);
	 #10000 $stop;
	end

	 $display("instruction ;%s is loading ...",str);
	    //$display("4: str: %h",str1);		 
	if(command=="add") begin
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);
	  get_reg(str3,str4,rg3_o); 
	  ld_instr({ADD,rg1_o,rg2_o,rg3_o,6'b0});
	end else if (command=="sub") begin
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);
	  get_reg(str3,str4,rg3_o); 
	  ld_instr({SUB,rg1_o,rg2_o,rg3_o,6'b0});
	end else if (command=="adi") begin
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);
	  get_reg(str3,str4,rg3_o); 
	  ld_instr({ADI,rg1_o,rg2_o,rg3_o,6'b0});
	end else if (command=="sbi") begin
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);
	  get_reg(str3,str4,rg3_o); 
	  ld_instr({SBI,rg1_o,rg2_o,rg3_o,6'b0});
	end else if (command=="sub") begin
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);
	  get_reg(str3,str4,rg3_o); 
	  ld_instr({ADD,rg1_o,rg2_o,rg3_o,6'b0});
	end else if (command=="anm") begin
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);
	  get_reg(str3,str4,rg3_o); 
	  ld_instr({ANM,rg1_o,rg2_o,rg3_o,6'b0});
	end else if (command=="orm") begin
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);
	  get_reg(str3,str4,rg3_o); 
	  ld_instr({ORM,rg1_o,rg2_o,rg3_o,6'b0});
	end else if (command=="anp") begin
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);
	  get_reg(str3,str4,rg3_o); 
	  ld_instr({ANP,rg1_o,rg2_o,rg3_o,6'b0});
	end else if (command=="orr") begin
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);
	  get_reg(str3,str4,rg3_o); 
	  ld_instr({ORR,rg1_o,rg2_o,rg3_o,6'b0});
	end else if (command=="shl") begin
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);
	  getdata(str3); 
	  ld_instr({SHL,rg1_o,rg2_o,data});
	end else if (command=="shr") begin
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);
	  getdata(str3); 
	  ld_instr({SHR ,rg1_o,rg2_o,data});
	end else if (command=="lbm") begin
	    //$display("2: str: %h",str1);
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);
	  ld_instr({LBM,rg1_o,rg2_o,8'b0});
	end else if (command=="sbm") begin
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);

	  ld_instr({SBM,rg1_o,rg2_o,8'b0});
	end else if (command=="mov") begin
	  get_reg(str1,str2,rg1_o);
	  getdata(str2);
	  ld_instr({MOV,rg1_o,2'b0,data});
	end else if (command=="jeq") begin
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);
	  getdata(str3); 
	  ld_instr({JEQ,rg1_o,rg2_o,data});
	end else if (command=="jls") begin
	  get_reg(str1,str2,rg1_o);
	  get_reg(str2,str3,rg2_o);
	  getdata(str3); 
	  ld_instr({JLS,rg1_o,rg2_o,data});
	end else if (command=="jmp") begin
	  getdata(str1); 
	  ld_instr({JMP,4'b0,data});
	end else ;
		end //read_program in
	end //initial

	task getcmd;
	input[127:0] str;
	output[127:0] str1;
	integer i;
	reg[127:0] str1;
	begin

	//cmd must be 3 characters
	begin:gmd1
	for(i=0;i<=127;i=i+1)
	 if (str[127]==1'b0) begin
	   str=str<<1;
	end else if (str[127]==1'b1) begin
		command={1'b0,str[127:127-23+1]};
		disable gmd1;
		end
	end	
	//$display("str:%b",str);
	//cut the cmd 23 bits 
	for (i=0;i<=22;i=i+1)
	   str=str<<1;
	//remove the possible space
	remove_space(str,str1);
	//$display("in getcmd str: %h",str);
	reg1=str[127:127-15];

	reg2=str[127-24:127-24-15];
	end
	endtask

	task get_reg;
	input [127:0] str;
	output[127:0] str1;
	output[1:0] rg_o;
	reg  [127:0] str0;
	reg[1:0] rg_o;

	begin
	    reg1=str[127:127-15];
	    //display("in get_reg: %h", reg1[3:0]);

	    if (reg1[3:0]==4'h0) rg_o=2'b00;
	    else if (reg1[3:0]==4'h1) rg_o=2'b01;
	    else if (reg1[3:0]==4'h2) rg_o=2'b10;
	    else if (reg1[3:0]==4'h3) rg_o=2'b11;

	for(i=0;i<=23;i=i+1)	    
	   str=str<<1;
	   remove_space(str,str0);
	   str1=str0;
	end
	endtask

	task remove_space;
	input [127:0] str;
	output[127:0] str1;

	reg  [127:0] str1;
	begin 
	  while(str[127:127-8+1]==8'h20)
		begin
		  for(i=0;i<=7;i=i+1)
	          str=str<<1;
		end

	          str1=str;
		end
	endtask

	task getdata;
	input [127:0] str;
	reg[3:0] chac1,chac2;
	begin
	  data_byte=str[127:127-15];
	  //$display("getdata: str:%h data byte %h",str,data_byte);
	  getchac(data_byte[15:8],chac1);
	  getchac(data_byte[7:0],chac2);
	  data=chac1*16+chac2;
	  //$display("getdata: chac1:%h =>data %h",chac1,data);
	end
	endtask

	task getchac;
	input [7:0] data_byte;
	output [3:0] chac;
	reg[3:0] chac;
        begin
	  if(data_byte==8'h61) chac=4'ha;
	  else if(data_byte==8'h62) chac=4'hb;
	  else if(data_byte==8'h63) chac=4'hc;
	  else if(data_byte==8'h64) chac=4'hd;
	  else if(data_byte==8'h65) chac=4'he;
	  else if(data_byte==8'h66) chac=4'hf;
	  else if(data_byte==8'h31) chac=4'h1;
	  else if(data_byte==8'h32) chac=4'h2;
	  else if(data_byte==8'h33) chac=4'h3;
	  else if(data_byte==8'h34) chac=4'h4;
	  else if(data_byte==8'h35) chac=4'h5;
	  else if(data_byte==8'h36) chac=4'h6;
	  else if(data_byte==8'h37) chac=4'h7;
	  else if(data_byte==8'h38) chac=4'h8;
	  else if(data_byte==8'h39) chac=4'h9;
	  else chac=4'h0;
	end
	endtask

	task ld_instr;
	input[15:0] din;
	begin
	  iowen=0;
	  dout=din[15:8];
	  $display("addr=%h ",addr);
	  @(posedge clk);
	  addr=#1 addr+1;
	  iowen=1;
	end
	endtask

 endmodule