default-1.cfg

精通verilog HDL语言编程的一个不错的cpu 代码

# Virsim Configuration File
version "2.2.0"

# Files Open:
#   Designator  Sources  Filename
#   ----------  -------  --------
#       I1         y     Interactive

define language Verilog;

define exprgroup EGroup0;

define linkwindow SIM
	time 50000 "10 ps",
	exprgroup "EGroup0";

define group "AutoGroup0"
	verticalposition 1,
	add "I1" "test_cpu.ATPG" "strength" 1 ,
	add "I1" "test_cpu.clk" "strength" 1 ,
	add "I1" "test_cpu.ioaddr" "hex" 1 ,
	add "I1" "test_cpu.iodata" "hex" 1 ,
	add "I1" "test_cpu.iowen" "strength" 1 ,
	add "I1" "test_cpu.load" "strength" 1 ,
	add "I1" "test_cpu.nrst" "strength" 1 ;