verilog.log

精通verilog HDL语言编程的一个不错的cpu 代码

Host command: /export/home/cad/LDV41/tools/verilog/bin/verilog.exe
Command arguments:
    CPU.v
    alu.v
    test_cpu.v
    IO.v
    control.v
    memory.v

Tool:	VERILOG-XL	04.10.001-p log file created Feb 15, 2009  19:57:48
Tool:	VERILOG-XL	04.10.001-p   Feb 15, 2009  19:57:48

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Compiling source file "CPU.v"

Error!    Identifier (clki) not declared                    [Verilog-IDSND]    
          "CPU.v", 32: 
Compiling source file "alu.v"
Compiling source file "test_cpu.v"

Error!    Task or function ($fsdbDumpvars) not defined      [Verilog-TOFD]     
          "test_cpu.v", 36: 

Error!    Identifier (top) not declared                     [Verilog-IDSND]    
          "test_cpu.v", 36: 
Compiling source file "IO.v"

Error!    syntax error                                      [Verilog]          
          "IO.v", 34: reg[7:0]   data,addr=<-

Error!    syntax error                                      [Verilog]          
          "IO.v", 38: reg	   load=<-

Error!    syntax error                                      [Verilog]          
          "IO.v", 39: reg        iowen=<-

Error!    Task or function ($fgets) not defined             [Verilog-TOFD]     
          "IO.v", 60: 
Compiling source file "control.v"
Compiling source file "memory.v"
7 errors
End of Tool:	VERILOG-XL	04.10.001-p   Feb 15, 2009  19:57:56