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精通verilog HDL语言编程的一个不错的cpu 代码

//**store to mem 

mov r3 f0
sbm r3 r0
//compare 
jls r1 r0 10 
mov r0 48 
mov r1 0d
mov r2 01
anp r3 r1 r2 
jeq r3 r2 00
mov r3 00
mov r0 00
//**store to mem 

mov r3 f1
sbm r3 r0
//compare 
jls r1 r0 22
mov r0 48 
mov r2 02
anp r3 r1 r2 
jeq r3 r2 14
mov r3 00
mov r0 00
//**store to mem 

mov r3 f2
sbm r3 r0
//compare 
jls r1 r0 34
mov r0 48 
mov r2 04
anp r3 r1 r2 
jeq r3 r2 26
mov r3 00
mov r0 00
//**store to mem 

mov r3 f3
sbm r3 r0
//compare 
jls r1 r0 46
mov r0 48 
mov r2 08
anp r3 r1 r2 
jeq r3 r2 38
end