readme.doc

来自「opencore ahb to wishbone bus verilog cod」· DOC 代码 · 共 58 行

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//*****************************************************************************************************************
// Copyright (c) 2007 TooMuch Semiconductor Solutions Pvt Ltd.
//
//File name		:	Readme.doc	
//Designer		: 	Sanjay kumar	
//Date			: 	3rd Aug'2007		
//Description		: 	List of files for system verilog testbench using AVM.
//Revision		:	1.0
//*****************************************************************************************************************
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////

//*****************************
//avm_svtb, includes svtb files
//*****************************
 
//The file consists of request,response and monitor package.
global.sv 

// interface 
ahb_wb_interface.sv

// set of class used as an operational components
ahb_wb_stim_gen.svh
ahb_wb_driver.svh
ahb_wb_responder.svh

// set of class used as an analysis components 
ahb_wb_monitor.svh
ahb_wb_scoreboard.svh
ahb_wb_coverage.svh

// Enviornment class
ahb_wb_env.svh

// modules 
ahb_wb_master.sv
ahb_wb_top.sv

//***********************************
//sim_svtb, includes simulation files
//***********************************

//package include all the classes 
ahb_wb_pkg.sv

// list of files 
// library files are not included 
// specify the respective avm library path in compile_sv.f
compile_sv.f

//compile and simulation commands without coverage
run.all
//compile and simulation commands with coverage
cov_run.all