s2p.v

来自「串并转换功能」· Verilog 代码 · 共 41 行

module s2p(rst,clk,s2p_en,data_in,data_out,data_out_valid);
	input rst,clk;
	input s2p_en;
	input data_in;
	output data_out_valid;
	output [3:0] data_out;
	reg  [3:0] data_out;
	reg data_out_valid;
	
	reg [1:0] counter;
	
	always @(posedge clk or negedge rst)
		if (!rst)
			counter<=2'b00;
		else if(counter==2'b11)
			counter<=2'b00;
		else 
			counter<=counter+2'b01;
		
		
	always @ (posedge clk or negedge rst)
		if (!rst)
			data_out<=4'h0;
		else if(s2p_en)
		begin
			data_out[0]<=data_in;
			data_out[3:1]<=data_out[2:0];
		end
		else 
			data_out<=4'h0;
		
	always@(posedge clk or negedge rst)
		if(!rst)
	  	 data_out_valid<=1'b0;
	  else if((counter==2'b11)&&(s2p_en))
	  	data_out_valid<=1'b1;
	  else
	  	data_out_valid<=1'b0;
	  

endmodule