reg32b.vhd

来自「数字频率计是一种用来测试周期性变化信号工作频率的装置。其原理是在规定的单位时间（」· VHDL 代码 · 共 21 行

library ieee;
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;
ENTITY REG32B   IS
PORT (LOAD:IN  STD_LOGIC;
DIN:IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END REG32B;
ARCHITECTURE  ART OF REG32B IS
SIGNAL REG32:STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
PROCESS(LOAD,DIN)
BEGIN
IF LOAD'EVENT AND LOAD='1' THEN
REG32<=DIN;
END IF;
END PROCESS;
DOUT<=REG32;
END ART;